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Searched refs:VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (Results 1 – 17 of 17) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/mcx_vbat/
Dfsl_vbat.c91 …>OSCCTLA = ((base->OSCCTLA & ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)) | in VBAT_SetCrystalOsc32kModeAndLoadCapacitance()
93 …>OSCCTLB = ((base->OSCCTLB & ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)) | in VBAT_SetCrystalOsc32kModeAndLoadCapacitance()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/drivers/
Dfsl_clock.c623 tmp32 &= ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK); in VBAT_SetOscConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/drivers/
Dfsl_clock.c623 tmp32 &= ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK); in VBAT_SetOscConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_clock.c639 tmp32 &= ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK); in VBAT_SetOscConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_clock.c639 tmp32 &= ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK); in VBAT_SetOscConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/
Dfsl_clock.c639 tmp32 &= ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK); in VBAT_SetOscConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/
Dfsl_clock.c639 tmp32 &= ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK); in VBAT_SetOscConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h67688 #define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (0xF000U) macro
67708 …(((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h67646 #define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (0xF000U) macro
67666 …(((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h88374 #define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (0xF000U) macro
88394 …(((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)
DMCXN546_cm33_core1.h88374 #define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (0xF000U) macro
88394 …(((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h88374 #define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (0xF000U) macro
88394 …(((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)
DMCXN547_cm33_core1.h88374 #define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (0xF000U) macro
88394 …(((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h91040 #define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (0xF000U) macro
91060 …(((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)
DMCXN947_cm33_core0.h91040 #define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (0xF000U) macro
91060 …(((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h91040 #define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (0xF000U) macro
91060 …(((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)
DMCXN946_cm33_core1.h91040 #define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (0xF000U) macro
91060 …(((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)