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Searched refs:UTICK0FCLKSEL_OFFSET (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.h811 #define UTICK0FCLKSEL_OFFSET 0x700 macro
1074 …CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 0), /*!< Attach compute base clock…
1075 …kLPOSC_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 1), /*!< Attach main_pll_pfd0 …
1076 …kFRO0_DIV1_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max to UT…
1077 …kFRO1_DIV2_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 3), /*!< Attach FRO1_DIV2 to U…
1078 …kNONE_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA_NONE(UTICK0FCLKSEL_OFFSET, 0), /*!< Attach NONE to U…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.h811 #define UTICK0FCLKSEL_OFFSET 0x700 macro
1074 …CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 0), /*!< Attach compute base clock…
1075 …kLPOSC_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 1), /*!< Attach main_pll_pfd0 …
1076 …kFRO0_DIV1_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max to UT…
1077 …kFRO1_DIV2_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 3), /*!< Attach FRO1_DIV2 to U…
1078 …kNONE_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA_NONE(UTICK0FCLKSEL_OFFSET, 0), /*!< Attach NONE to U…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.h811 #define UTICK0FCLKSEL_OFFSET 0x700 macro
1074 …CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 0), /*!< Attach compute base clock…
1075 …kLPOSC_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 1), /*!< Attach main_pll_pfd0 …
1076 …kFRO0_DIV1_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max to UT…
1077 …kFRO1_DIV2_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA(UTICK0FCLKSEL_OFFSET, 3), /*!< Attach FRO1_DIV2 to U…
1078 …kNONE_to_UTICK0_CLK = CLKCTL0_TUPLE_MUXA_NONE(UTICK0FCLKSEL_OFFSET, 0), /*!< Attach NONE to U…