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Searched refs:USDHC_MIX_CTRL_NIBBLE_POS_MASK (Results 1 – 25 of 119) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_USDHC.h1002 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
1005 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/drivers/usdhc/
Dfsl_usdhc.c1134 base->MIX_CTRL &= ~USDHC_MIX_CTRL_NIBBLE_POS_MASK; in USDHC_EnableDDRMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm4.h24381 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
24384 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
DK32L3A60_cm0plus.h24491 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
24494 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h33178 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
33181 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
DMIMXRT685S_cm33.h44134 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
44137 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h40521 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
40524 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h40522 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
40525 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h44134 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
44137 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h48835 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
48838 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
DMIMXRT595S_cm33.h59880 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
59883 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h43213 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
43216 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h43234 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
43237 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h45333 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
45336 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h46297 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
46300 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h49599 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
49602 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h49707 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
49710 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h58253 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
58256 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h47688 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
47691 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h54593 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
54595 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h54591 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
54593 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h54591 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
54593 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h62046 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
62049 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h54593 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
54595 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h59879 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) macro
59882 …(((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)

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