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Searched refs:USDHC_CMD_RSP2_CMDRSP2_MASK (Results 1 – 25 of 118) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_USDHC.h284 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
287 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm4.h23363 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
23366 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
DK32L3A60_cm0plus.h23473 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
23476 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h32022 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
32025 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
DMIMXRT685S_cm33.h42978 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
42981 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h39359 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
39362 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h39360 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
39363 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h42978 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
42981 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h47681 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
47684 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
DMIMXRT595S_cm33.h58726 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
58729 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h42098 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
42101 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h42119 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
42122 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h44180 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
44183 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h45182 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
45185 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h48446 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
48449 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h48592 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
48595 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h57099 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
57102 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h46573 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
46576 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h53412 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
53416 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h53410 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
53414 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h53410 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
53414 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h60949 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
60952 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
DMIMXRT735S_cm33_core1.h61016 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
61019 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h53412 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
53416 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h58725 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) macro
58728 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)

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