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Searched refs:USDHC_CMD_RSP1_CMDRSP1_MASK (Results 1 – 25 of 118) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_USDHC.h275 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
278 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm4.h23354 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
23357 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
DK32L3A60_cm0plus.h23464 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
23467 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h32013 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
32016 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
DMIMXRT685S_cm33.h42969 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
42972 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h39350 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
39353 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h39351 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
39354 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h42969 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
42972 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h47672 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
47675 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
DMIMXRT595S_cm33.h58717 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
58720 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h42089 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
42092 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h42110 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
42113 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h44171 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
44174 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h45173 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
45176 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h48437 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
48440 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h48583 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
48586 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h57090 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
57093 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h46564 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
46567 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h53402 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
53406 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h53400 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
53404 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h53400 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
53404 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h60940 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
60943 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
DMIMXRT735S_cm33_core1.h61007 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
61010 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h53402 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
53406 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h58716 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) macro
58719 … (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)

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