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Searched refs:TSM_REG_VALUE (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/
Dtsm_ll_timing.c121 TSM_REG_VALUE(PLL_REG_EN_RX_WD, PLL_REG_EN_RX_WU, PLL_REG_EN_TX_WD, PLL_REG_EN_TX_WU),
122 …TSM_REG_VALUE(PLL_VCO_REG_EN_RX_WD, PLL_VCO_REG_EN_RX_WU, PLL_VCO_REG_EN_TX_WD, PLL_VCO_REG_EN_TX_…
123 …TSM_REG_VALUE(PLL_QGEN_REG_EN_RX_WD, PLL_QGEN_REG_EN_RX_WU, PLL_QGEN_REG_EN_TX_WD, PLL_QGEN_REG_EN…
124 …TSM_REG_VALUE(PLL_TCA_TX_REG_EN_RX_WD, PLL_TCA_TX_REG_EN_RX_WU, PLL_TCA_TX_REG_EN_TX_WD, PLL_TCA_T…
125 TSM_REG_VALUE(ADC_REG_EN_RX_WD, ADC_REG_EN_RX_WU, ADC_REG_EN_TX_WD, ADC_REG_EN_TX_WU),
126 …TSM_REG_VALUE(PLL_REF_CLK_EN_RX_WD, PLL_REF_CLK_EN_RX_WU, PLL_REF_CLK_EN_TX_WD, PLL_REF_CLK_EN_TX_…
127 TSM_REG_VALUE(ADC_CLK_EN_RX_WD, ADC_CLK_EN_RX_WU, ADC_CLK_EN_TX_WD, ADC_CLK_EN_TX_WU),
128 …TSM_REG_VALUE(PLL_VCO_AUTOTUNE_RX_WD, PLL_VCO_AUTOTUNE_RX_WU, PLL_VCO_AUTOTUNE_TX_WD, PLL_VCO_AUTO…
129 …TSM_REG_VALUE(PLL_CYCLE_SLIP_LD_EN_RX_WD, PLL_CYCLE_SLIP_LD_EN_RX_WU, PLL_CYCLE_SLIP_LD_EN_TX_WD, …
130 TSM_REG_VALUE(PLL_VCO_EN_RX_WD, PLL_VCO_EN_RX_WU, PLL_VCO_EN_TX_WD, PLL_VCO_EN_TX_WU),
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DKW4xXcvrDrv.c409 … XCVR_TSM_TIMING42 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, 0xFF)); /* Disabled TSM signal */ in XcvrFadLppsControl()
410 … XCVR_TSM_TIMING43 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, 0xFF)); /* Disabled TSM signal */ in XcvrFadLppsControl()
416 XCVR_TSM_TIMING42 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, END_OF_TX_WU_BLE)); in XcvrFadLppsControl()
417 XCVR_TSM_TIMING43 = (uint32_t)(TSM_REG_VALUE(0xFF, END_OF_RX_WU_BLE, 0xFF, 0xFF)); in XcvrFadLppsControl()
423 … XCVR_TSM_TIMING42 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, 0xFF)); /* Disabled TSM signal */ in XcvrFadLppsControl()
424 … XCVR_TSM_TIMING43 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, 0xFF)); /* Disabled TSM signal */ in XcvrFadLppsControl()
Dtsm_timing_ble.h65 #define TSM_REG_VALUE(rx_wd,rx_wu,tx_wd,tx_wu) ((((unsigned int)rx_wd<<TSM_RX_LO_SHIFT)&TSM_RX_LO_M… macro