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Searched refs:TSHD (Results 1 – 25 of 39) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/tsi/
Dfsl_tsi_v4.h581 base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESL_MASK) | (TSI_TSHD_THRESL(low_threshold)); in TSI_SetLowThreshold()
595 base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESH_MASK) | (TSI_TSHD_THRESH(high_threshold)); in TSI_SetHighThreshold()
Dfsl_tsi_v5.h965 base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESL_MASK) | (TSI_TSHD_THRESL(low_threshold)); in TSI_SetLowThreshold()
977 base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESH_MASK) | (TSI_TSHD_THRESH(high_threshold)); in TSI_SetHighThreshold()
Dfsl_tsi_v4.c92 base->TSHD = 0U; in TSI_Deinit()
Dfsl_tsi_v5.c210 base->TSHD = 0U; in TSI_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/drivers/tsi/tsi_v4/
Dfsl_tsi_v4.h581 base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESL_MASK) | (TSI_TSHD_THRESL(low_threshold)); in TSI_SetLowThreshold()
595 base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESH_MASK) | (TSI_TSHD_THRESH(high_threshold)); in TSI_SetHighThreshold()
Dfsl_tsi_v4.c92 base->TSHD = 0U; in TSI_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/drivers/tsi/tsi_v6/
Dfsl_tsi_v6.h933 base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESL_MASK) | (TSI_TSHD_THRESL(low_threshold)); in TSI_SetLowThreshold()
945 base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESH_MASK) | (TSI_TSHD_THRESH(high_threshold)); in TSI_SetHighThreshold()
Dfsl_tsi_v6.c209 base->TSHD = 0U; in TSI_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/drivers/tsi/tsi_v5/
Dfsl_tsi_v5.h1024 base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESL_MASK) | (TSI_TSHD_THRESL(low_threshold)); in TSI_SetLowThreshold()
1036 base->TSHD = ((base->TSHD) & ~TSI_TSHD_THRESH_MASK) | (TSI_TSHD_THRESH(high_threshold)); in TSI_SetHighThreshold()
Dfsl_tsi_v5.c217 base->TSHD = 0U; in TSI_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/
DMKL25Z4.h4347 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h10973 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h8873 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ member
8889 #define TSI_TSHD_REG(base) ((base)->TSHD)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/
DMKW20Z4.h8873 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ member
8889 #define TSI_TSHD_REG(base) ((base)->TSHD)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/
DMKW40Z4.h8873 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ member
8889 #define TSI_TSHD_REG(base) ((base)->TSHD)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h11810 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/
DMKE17Z7.h13674 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h13670 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/
DMKE17Z9.h13645 __IO uint32_t TSHD; /**< TSI threshold register, offset: 0x8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h13885 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/
DMKE13Z9.h13642 __IO uint32_t TSHD; /**< TSI threshold register, offset: 0x8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h17705 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h17705 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW31Z4/
DMKW31Z4.h7761 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW21Z4/
DMKW21Z4.h7690 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ member

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