1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_TRGMUX.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_TRGMUX 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_TRGMUX_H_) /* Check if memory map has not been already included */ 58 #define S32K344_TRGMUX_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- TRGMUX Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer 68 * @{ 69 */ 70 71 /** TRGMUX - Size of Registers Arrays */ 72 #define TRGMUX_TRGMUXn_COUNT 40u 73 74 /** TRGMUX - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t TRGMUXn[TRGMUX_TRGMUXn_COUNT]; /**< TRGMUX ADC12_0 Register..TRGMUX CM7_RXEV Register, array offset: 0x0, array step: 0x4 */ 77 } TRGMUX_Type, *TRGMUX_MemMapPtr; 78 79 /** Number of instances of the TRGMUX module. */ 80 #define TRGMUX_INSTANCE_COUNT (1) 81 82 /* TRGMUX - Peripheral instance base addresses */ 83 /** Peripheral TRGMUX base address */ 84 #define IP_TRGMUX_BASE (0x40080000u) 85 /** Peripheral TRGMUX base pointer */ 86 #define IP_TRGMUX ((TRGMUX_Type *)IP_TRGMUX_BASE) 87 /** Array initializer of TRGMUX peripheral base addresses */ 88 #define IP_TRGMUX_BASE_ADDRS { IP_TRGMUX_BASE } 89 /** Array initializer of TRGMUX peripheral base pointers */ 90 #define IP_TRGMUX_BASE_PTRS { IP_TRGMUX } 91 92 /* ---------------------------------------------------------------------------- 93 -- TRGMUX Register Masks 94 ---------------------------------------------------------------------------- */ 95 96 /*! 97 * @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks 98 * @{ 99 */ 100 101 /*! @name TRGMUXn - TRGMUX ADC12_0 Register..TRGMUX CM7_RXEV Register */ 102 /*! @{ */ 103 104 #define TRGMUX_TRGMUXn_SEL0_MASK (0x7FU) 105 #define TRGMUX_TRGMUXn_SEL0_SHIFT (0U) 106 #define TRGMUX_TRGMUXn_SEL0_WIDTH (7U) 107 #define TRGMUX_TRGMUXn_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGMUXn_SEL0_SHIFT)) & TRGMUX_TRGMUXn_SEL0_MASK) 108 109 #define TRGMUX_TRGMUXn_SEL1_MASK (0x7F00U) 110 #define TRGMUX_TRGMUXn_SEL1_SHIFT (8U) 111 #define TRGMUX_TRGMUXn_SEL1_WIDTH (7U) 112 #define TRGMUX_TRGMUXn_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGMUXn_SEL1_SHIFT)) & TRGMUX_TRGMUXn_SEL1_MASK) 113 114 #define TRGMUX_TRGMUXn_SEL2_MASK (0x7F0000U) 115 #define TRGMUX_TRGMUXn_SEL2_SHIFT (16U) 116 #define TRGMUX_TRGMUXn_SEL2_WIDTH (7U) 117 #define TRGMUX_TRGMUXn_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGMUXn_SEL2_SHIFT)) & TRGMUX_TRGMUXn_SEL2_MASK) 118 119 #define TRGMUX_TRGMUXn_SEL3_MASK (0x7F000000U) 120 #define TRGMUX_TRGMUXn_SEL3_SHIFT (24U) 121 #define TRGMUX_TRGMUXn_SEL3_WIDTH (7U) 122 #define TRGMUX_TRGMUXn_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGMUXn_SEL3_SHIFT)) & TRGMUX_TRGMUXn_SEL3_MASK) 123 124 #define TRGMUX_TRGMUXn_LK_MASK (0x80000000U) 125 #define TRGMUX_TRGMUXn_LK_SHIFT (31U) 126 #define TRGMUX_TRGMUXn_LK_WIDTH (1U) 127 #define TRGMUX_TRGMUXn_LK(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGMUXn_LK_SHIFT)) & TRGMUX_TRGMUXn_LK_MASK) 128 /*! @} */ 129 130 /*! 131 * @} 132 */ /* end of group TRGMUX_Register_Masks */ 133 #define TRGMUX_ADC12_0_INDEX 0 134 #define TRGMUX_ADC12_1_INDEX 1 135 #define TRGMUX_ADC12_2_INDEX 2 136 #define TRGMUX_LPCMP_0_INDEX 3 137 #define TRGMUX_LPCMP_1_INDEX 4 138 #define TRGMUX_LPCMP_2_INDEX 5 139 #define TRGMUX_BCTU_INDEX 6 140 #define TRGMUX_eMIOS012_ODIS_INDEX 7 141 #define TRGMUX_eMIOS0_0_INDEX 8 142 #define TRGMUX_eMIOS0_1_INDEX 9 143 #define TRGMUX_eMIOS0_2_INDEX 10 144 #define TRGMUX_eMIOS0_3_INDEX 11 145 #define TRGMUX_eMIOS1_0_INDEX 12 146 #define TRGMUX_eMIOS1_1_INDEX 13 147 #define TRGMUX_eMIOS1_2_INDEX 14 148 #define TRGMUX_eMIOS1_3_INDEX 15 149 #define TRGMUX_FlexIO_INDEX 16 150 #define TRGMUX_SIUL_OUT0_INDEX 17 151 #define TRGMUX_SIUL_OUT1_INDEX 18 152 #define TRGMUX_SIUL_OUT2_INDEX 19 153 #define TRGMUX_SIUL_OUT3_INDEX 20 154 #define TRGMUX_LPI2C_0_INDEX 21 155 #define TRGMUX_LPSPI_0_INDEX 22 156 #define TRGMUX_LPSPI_1_INDEX 23 157 #define TRGMUX_LPSPI_2_INDEX 24 158 #define TRGMUX_LPUART_0_INDEX 25 159 #define TRGMUX_LPUART_1_INDEX 26 160 #define TRGMUX_LPUART_2_INDEX 27 161 #define TRGMUX_LPUART_3_INDEX 28 162 #define TRGMUX_LCU0_SYNC_INDEX 29 163 #define TRGMUX_LCU0_FORCE_INDEX 30 164 #define TRGMUX_LCU0_0_INDEX 31 165 #define TRGMUX_LCU0_1_INDEX 32 166 #define TRGMUX_LCU0_2_INDEX 33 167 #define TRGMUX_LCU1_SYNC_INDEX 34 168 #define TRGMUX_LCU1_FORCE_INDEX 35 169 #define TRGMUX_LCU1_0_INDEX 36 170 #define TRGMUX_LCU1_1_INDEX 37 171 #define TRGMUX_LCU1_2_INDEX 38 172 #define TRGMUX_CM7_RXEV_INDEX 39 173 174 175 /*! 176 * @} 177 */ /* end of group TRGMUX_Peripheral_Access_Layer */ 178 179 #endif /* #if !defined(S32K344_TRGMUX_H_) */ 180
