1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2024 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32Z2_TRGMUX_3.h
10  * @version 2.3
11  * @date 2024-05-03
12  * @brief Peripheral Access Layer for S32Z2_TRGMUX_3
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32Z2_TRGMUX_3_H_)  /* Check if memory map has not been already included */
58 #define S32Z2_TRGMUX_3_H_
59 
60 #include "S32Z2_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- TRGMUX_3 Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup TRGMUX_3_Peripheral_Access_Layer TRGMUX_3 Peripheral Access Layer
68  * @{
69  */
70 
71 /** TRGMUX_3 - Register Layout Typedef */
72 typedef struct {
73   __IO uint32_t GTM_003_000;                       /**< TRGMUX GTM_003_000, offset: 0x0 */
74   __IO uint32_t GTM_007_004;                       /**< TRGMUX GTM_007_004, offset: 0x4 */
75   __IO uint32_t GTM_011_008;                       /**< TRGMUX GTM_011_008, offset: 0x8 */
76   __IO uint32_t GTM_015_012;                       /**< TRGMUX GTM_015_012, offset: 0xC */
77   __IO uint32_t GTM_019_016;                       /**< TRGMUX GTM_019_016, offset: 0x10 */
78   __IO uint32_t GTM_023_020;                       /**< TRGMUX GTM_023_020, offset: 0x14 */
79   __IO uint32_t GTM_027_024;                       /**< TRGMUX GTM_027_024, offset: 0x18 */
80   __IO uint32_t GTM_031_028;                       /**< TRGMUX GTM_031_028, offset: 0x1C */
81   __IO uint32_t GTM_035_032;                       /**< TRGMUX GTM_035_032, offset: 0x20 */
82   __IO uint32_t GTM_039_036;                       /**< TRGMUX GTM_039_036, offset: 0x24 */
83   __IO uint32_t GTM_043_040;                       /**< TRGMUX GTM_043_040, offset: 0x28 */
84   __IO uint32_t GTM_047_044;                       /**< TRGMUX GTM_047_044, offset: 0x2C */
85   __IO uint32_t GTM_051_048;                       /**< TRGMUX GTM_051_048, offset: 0x30 */
86   __IO uint32_t GTM_055_052;                       /**< TRGMUX GTM_055_052, offset: 0x34 */
87   __IO uint32_t GTM_059_056;                       /**< TRGMUX GTM_059_056, offset: 0x38 */
88   __IO uint32_t GTM_063_060;                       /**< TRGMUX GTM_063_060, offset: 0x3C */
89   __IO uint32_t GTM_067_064;                       /**< TRGMUX GTM_067_064, offset: 0x40 */
90   __IO uint32_t GTM_071_068;                       /**< TRGMUX GTM_071_068, offset: 0x44 */
91   __IO uint32_t GTM_075_072;                       /**< TRGMUX GTM_075_072, offset: 0x48 */
92   __IO uint32_t GTM_079_076;                       /**< TRGMUX GTM_079_076, offset: 0x4C */
93   __IO uint32_t GTM_083_080;                       /**< TRGMUX GTM_083_080, offset: 0x50 */
94   __IO uint32_t GTM_087_084;                       /**< TRGMUX GTM_087_084, offset: 0x54 */
95   __IO uint32_t GTM_091_088;                       /**< TRGMUX GTM_091_088, offset: 0x58 */
96   __IO uint32_t GTM_095_092;                       /**< TRGMUX GTM_095_092, offset: 0x5C */
97   __IO uint32_t GTM_099_096;                       /**< TRGMUX GTM_099_096, offset: 0x60 */
98   __IO uint32_t GTM_103_100;                       /**< TRGMUX GTM_103_100, offset: 0x64 */
99   __IO uint32_t GTM_107_104;                       /**< TRGMUX GTM_107_104, offset: 0x68 */
100   __IO uint32_t GTM_111_108;                       /**< TRGMUX GTM_111_108, offset: 0x6C */
101   __IO uint32_t GTM_115_112;                       /**< TRGMUX GTM_115_112, offset: 0x70 */
102   __IO uint32_t GTM_119_116;                       /**< TRGMUX GTM_119_116, offset: 0x74 */
103   __IO uint32_t GTM_123_120;                       /**< TRGMUX GTM_123_120, offset: 0x78 */
104   __IO uint32_t GTM_127_124;                       /**< TRGMUX GTM_127_124, offset: 0x7C */
105   __IO uint32_t GTM_131_128;                       /**< TRGMUX GTM_131_128, offset: 0x80 */
106   __IO uint32_t GTM_135_132;                       /**< TRGMUX GTM_135_132, offset: 0x84 */
107   __IO uint32_t GTM_139_136;                       /**< TRGMUX GTM_139_136, offset: 0x88 */
108   __IO uint32_t GTM_143_140;                       /**< TRGMUX GTM_143_140, offset: 0x8C */
109   __IO uint32_t GTM_147_144;                       /**< TRGMUX GTM_147_144, offset: 0x90 */
110   __IO uint32_t GTM_151_148;                       /**< TRGMUX GTM_151_148, offset: 0x94 */
111   __IO uint32_t GTM_155_152;                       /**< TRGMUX GTM_155_152, offset: 0x98 */
112   __IO uint32_t GTM_159_156;                       /**< TRGMUX GTM_159_156, offset: 0x9C */
113   __IO uint32_t GTM_163_160;                       /**< TRGMUX GTM_163_160, offset: 0xA0 */
114   __IO uint32_t GTM_167_164;                       /**< TRGMUX GTM_167_164, offset: 0xA4 */
115   __IO uint32_t GTM_168;                           /**< TRGMUX GTM_168, offset: 0xA8 */
116   __IO uint32_t MSC_03_00;                         /**< TRGMUX MSC_03_00, offset: 0xAC */
117   __IO uint32_t MSC_07_04;                         /**< TRGMUX MSC_07_04, offset: 0xB0 */
118   __IO uint32_t MSC_11_08;                         /**< TRGMUX MSC_11_08, offset: 0xB4 */
119   __IO uint32_t MSC_15_12;                         /**< TRGMUX MSC_15_12, offset: 0xB8 */
120   __IO uint32_t MSC_19_16;                         /**< TRGMUX MSC_19_16, offset: 0xBC */
121   __IO uint32_t MSC_23_20;                         /**< TRGMUX MSC_23_20, offset: 0xC0 */
122   __IO uint32_t MSC_27_24;                         /**< TRGMUX MSC_27_24, offset: 0xC4 */
123   __IO uint32_t MSC_31_28;                         /**< TRGMUX MSC_31_28, offset: 0xC8 */
124   __IO uint32_t MSC_35_32;                         /**< TRGMUX MSC_35_32, offset: 0xCC */
125   __IO uint32_t MSC_39_36;                         /**< TRGMUX MSC_39_36, offset: 0xD0 */
126   __IO uint32_t MSC_43_40;                         /**< TRGMUX MSC_43_40, offset: 0xD4 */
127   __IO uint32_t MSC_47_44;                         /**< TRGMUX MSC_47_44, offset: 0xD8 */
128   __IO uint32_t MSC_51_48;                         /**< TRGMUX MSC_51_48, offset: 0xDC */
129   __IO uint32_t MSC_55_52;                         /**< TRGMUX MSC_55_52, offset: 0xE0 */
130   __IO uint32_t MSC_59_56;                         /**< TRGMUX MSC_59_56, offset: 0xE4 */
131   __IO uint32_t MSC_63_60;                         /**< TRGMUX MSC_63_60, offset: 0xE8 */
132   __IO uint32_t CTU_3_0;                           /**< TRGMUX CTU_3_0, offset: 0xEC */
133   __IO uint32_t SINC_3_0;                          /**< TRGMUX SINC_3_0, offset: 0xF0 */
134 } TRGMUX_3_Type, *TRGMUX_3_MemMapPtr;
135 
136 /** Number of instances of the TRGMUX_3 module. */
137 #define TRGMUX_3_INSTANCE_COUNT                  (1u)
138 
139 /* TRGMUX_3 - Peripheral instance base addresses */
140 /** Peripheral TRGMUX_3 base address */
141 #define IP_TRGMUX_3_BASE                         (0x40372000u)
142 /** Peripheral TRGMUX_3 base pointer */
143 #define IP_TRGMUX_3                              ((TRGMUX_3_Type *)IP_TRGMUX_3_BASE)
144 /** Array initializer of TRGMUX_3 peripheral base addresses */
145 #define IP_TRGMUX_3_BASE_ADDRS                   { IP_TRGMUX_3_BASE }
146 /** Array initializer of TRGMUX_3 peripheral base pointers */
147 #define IP_TRGMUX_3_BASE_PTRS                    { IP_TRGMUX_3 }
148 
149 /* ----------------------------------------------------------------------------
150    -- TRGMUX_3 Register Masks
151    ---------------------------------------------------------------------------- */
152 
153 /*!
154  * @addtogroup TRGMUX_3_Register_Masks TRGMUX_3 Register Masks
155  * @{
156  */
157 
158 /*! @name GTM_003_000 - TRGMUX GTM_003_000 */
159 /*! @{ */
160 
161 #define TRGMUX_3_GTM_003_000_SEL0_MASK           (0x7FU)
162 #define TRGMUX_3_GTM_003_000_SEL0_SHIFT          (0U)
163 #define TRGMUX_3_GTM_003_000_SEL0_WIDTH          (7U)
164 #define TRGMUX_3_GTM_003_000_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_003_000_SEL0_SHIFT)) & TRGMUX_3_GTM_003_000_SEL0_MASK)
165 
166 #define TRGMUX_3_GTM_003_000_SEL1_MASK           (0x7F00U)
167 #define TRGMUX_3_GTM_003_000_SEL1_SHIFT          (8U)
168 #define TRGMUX_3_GTM_003_000_SEL1_WIDTH          (7U)
169 #define TRGMUX_3_GTM_003_000_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_003_000_SEL1_SHIFT)) & TRGMUX_3_GTM_003_000_SEL1_MASK)
170 
171 #define TRGMUX_3_GTM_003_000_SEL2_MASK           (0x7F0000U)
172 #define TRGMUX_3_GTM_003_000_SEL2_SHIFT          (16U)
173 #define TRGMUX_3_GTM_003_000_SEL2_WIDTH          (7U)
174 #define TRGMUX_3_GTM_003_000_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_003_000_SEL2_SHIFT)) & TRGMUX_3_GTM_003_000_SEL2_MASK)
175 
176 #define TRGMUX_3_GTM_003_000_SEL3_MASK           (0x7F000000U)
177 #define TRGMUX_3_GTM_003_000_SEL3_SHIFT          (24U)
178 #define TRGMUX_3_GTM_003_000_SEL3_WIDTH          (7U)
179 #define TRGMUX_3_GTM_003_000_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_003_000_SEL3_SHIFT)) & TRGMUX_3_GTM_003_000_SEL3_MASK)
180 
181 #define TRGMUX_3_GTM_003_000_LK_MASK             (0x80000000U)
182 #define TRGMUX_3_GTM_003_000_LK_SHIFT            (31U)
183 #define TRGMUX_3_GTM_003_000_LK_WIDTH            (1U)
184 #define TRGMUX_3_GTM_003_000_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_003_000_LK_SHIFT)) & TRGMUX_3_GTM_003_000_LK_MASK)
185 /*! @} */
186 
187 /*! @name GTM_007_004 - TRGMUX GTM_007_004 */
188 /*! @{ */
189 
190 #define TRGMUX_3_GTM_007_004_SEL0_MASK           (0x7FU)
191 #define TRGMUX_3_GTM_007_004_SEL0_SHIFT          (0U)
192 #define TRGMUX_3_GTM_007_004_SEL0_WIDTH          (7U)
193 #define TRGMUX_3_GTM_007_004_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_007_004_SEL0_SHIFT)) & TRGMUX_3_GTM_007_004_SEL0_MASK)
194 
195 #define TRGMUX_3_GTM_007_004_SEL1_MASK           (0x7F00U)
196 #define TRGMUX_3_GTM_007_004_SEL1_SHIFT          (8U)
197 #define TRGMUX_3_GTM_007_004_SEL1_WIDTH          (7U)
198 #define TRGMUX_3_GTM_007_004_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_007_004_SEL1_SHIFT)) & TRGMUX_3_GTM_007_004_SEL1_MASK)
199 
200 #define TRGMUX_3_GTM_007_004_SEL2_MASK           (0x7F0000U)
201 #define TRGMUX_3_GTM_007_004_SEL2_SHIFT          (16U)
202 #define TRGMUX_3_GTM_007_004_SEL2_WIDTH          (7U)
203 #define TRGMUX_3_GTM_007_004_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_007_004_SEL2_SHIFT)) & TRGMUX_3_GTM_007_004_SEL2_MASK)
204 
205 #define TRGMUX_3_GTM_007_004_SEL3_MASK           (0x7F000000U)
206 #define TRGMUX_3_GTM_007_004_SEL3_SHIFT          (24U)
207 #define TRGMUX_3_GTM_007_004_SEL3_WIDTH          (7U)
208 #define TRGMUX_3_GTM_007_004_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_007_004_SEL3_SHIFT)) & TRGMUX_3_GTM_007_004_SEL3_MASK)
209 
210 #define TRGMUX_3_GTM_007_004_LK_MASK             (0x80000000U)
211 #define TRGMUX_3_GTM_007_004_LK_SHIFT            (31U)
212 #define TRGMUX_3_GTM_007_004_LK_WIDTH            (1U)
213 #define TRGMUX_3_GTM_007_004_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_007_004_LK_SHIFT)) & TRGMUX_3_GTM_007_004_LK_MASK)
214 /*! @} */
215 
216 /*! @name GTM_011_008 - TRGMUX GTM_011_008 */
217 /*! @{ */
218 
219 #define TRGMUX_3_GTM_011_008_SEL0_MASK           (0x7FU)
220 #define TRGMUX_3_GTM_011_008_SEL0_SHIFT          (0U)
221 #define TRGMUX_3_GTM_011_008_SEL0_WIDTH          (7U)
222 #define TRGMUX_3_GTM_011_008_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_011_008_SEL0_SHIFT)) & TRGMUX_3_GTM_011_008_SEL0_MASK)
223 
224 #define TRGMUX_3_GTM_011_008_SEL1_MASK           (0x7F00U)
225 #define TRGMUX_3_GTM_011_008_SEL1_SHIFT          (8U)
226 #define TRGMUX_3_GTM_011_008_SEL1_WIDTH          (7U)
227 #define TRGMUX_3_GTM_011_008_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_011_008_SEL1_SHIFT)) & TRGMUX_3_GTM_011_008_SEL1_MASK)
228 
229 #define TRGMUX_3_GTM_011_008_SEL2_MASK           (0x7F0000U)
230 #define TRGMUX_3_GTM_011_008_SEL2_SHIFT          (16U)
231 #define TRGMUX_3_GTM_011_008_SEL2_WIDTH          (7U)
232 #define TRGMUX_3_GTM_011_008_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_011_008_SEL2_SHIFT)) & TRGMUX_3_GTM_011_008_SEL2_MASK)
233 
234 #define TRGMUX_3_GTM_011_008_SEL3_MASK           (0x7F000000U)
235 #define TRGMUX_3_GTM_011_008_SEL3_SHIFT          (24U)
236 #define TRGMUX_3_GTM_011_008_SEL3_WIDTH          (7U)
237 #define TRGMUX_3_GTM_011_008_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_011_008_SEL3_SHIFT)) & TRGMUX_3_GTM_011_008_SEL3_MASK)
238 
239 #define TRGMUX_3_GTM_011_008_LK_MASK             (0x80000000U)
240 #define TRGMUX_3_GTM_011_008_LK_SHIFT            (31U)
241 #define TRGMUX_3_GTM_011_008_LK_WIDTH            (1U)
242 #define TRGMUX_3_GTM_011_008_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_011_008_LK_SHIFT)) & TRGMUX_3_GTM_011_008_LK_MASK)
243 /*! @} */
244 
245 /*! @name GTM_015_012 - TRGMUX GTM_015_012 */
246 /*! @{ */
247 
248 #define TRGMUX_3_GTM_015_012_SEL0_MASK           (0x7FU)
249 #define TRGMUX_3_GTM_015_012_SEL0_SHIFT          (0U)
250 #define TRGMUX_3_GTM_015_012_SEL0_WIDTH          (7U)
251 #define TRGMUX_3_GTM_015_012_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_015_012_SEL0_SHIFT)) & TRGMUX_3_GTM_015_012_SEL0_MASK)
252 
253 #define TRGMUX_3_GTM_015_012_SEL1_MASK           (0x7F00U)
254 #define TRGMUX_3_GTM_015_012_SEL1_SHIFT          (8U)
255 #define TRGMUX_3_GTM_015_012_SEL1_WIDTH          (7U)
256 #define TRGMUX_3_GTM_015_012_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_015_012_SEL1_SHIFT)) & TRGMUX_3_GTM_015_012_SEL1_MASK)
257 
258 #define TRGMUX_3_GTM_015_012_SEL2_MASK           (0x7F0000U)
259 #define TRGMUX_3_GTM_015_012_SEL2_SHIFT          (16U)
260 #define TRGMUX_3_GTM_015_012_SEL2_WIDTH          (7U)
261 #define TRGMUX_3_GTM_015_012_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_015_012_SEL2_SHIFT)) & TRGMUX_3_GTM_015_012_SEL2_MASK)
262 
263 #define TRGMUX_3_GTM_015_012_SEL3_MASK           (0x7F000000U)
264 #define TRGMUX_3_GTM_015_012_SEL3_SHIFT          (24U)
265 #define TRGMUX_3_GTM_015_012_SEL3_WIDTH          (7U)
266 #define TRGMUX_3_GTM_015_012_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_015_012_SEL3_SHIFT)) & TRGMUX_3_GTM_015_012_SEL3_MASK)
267 
268 #define TRGMUX_3_GTM_015_012_LK_MASK             (0x80000000U)
269 #define TRGMUX_3_GTM_015_012_LK_SHIFT            (31U)
270 #define TRGMUX_3_GTM_015_012_LK_WIDTH            (1U)
271 #define TRGMUX_3_GTM_015_012_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_015_012_LK_SHIFT)) & TRGMUX_3_GTM_015_012_LK_MASK)
272 /*! @} */
273 
274 /*! @name GTM_019_016 - TRGMUX GTM_019_016 */
275 /*! @{ */
276 
277 #define TRGMUX_3_GTM_019_016_SEL0_MASK           (0x7FU)
278 #define TRGMUX_3_GTM_019_016_SEL0_SHIFT          (0U)
279 #define TRGMUX_3_GTM_019_016_SEL0_WIDTH          (7U)
280 #define TRGMUX_3_GTM_019_016_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_019_016_SEL0_SHIFT)) & TRGMUX_3_GTM_019_016_SEL0_MASK)
281 
282 #define TRGMUX_3_GTM_019_016_SEL1_MASK           (0x7F00U)
283 #define TRGMUX_3_GTM_019_016_SEL1_SHIFT          (8U)
284 #define TRGMUX_3_GTM_019_016_SEL1_WIDTH          (7U)
285 #define TRGMUX_3_GTM_019_016_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_019_016_SEL1_SHIFT)) & TRGMUX_3_GTM_019_016_SEL1_MASK)
286 
287 #define TRGMUX_3_GTM_019_016_SEL2_MASK           (0x7F0000U)
288 #define TRGMUX_3_GTM_019_016_SEL2_SHIFT          (16U)
289 #define TRGMUX_3_GTM_019_016_SEL2_WIDTH          (7U)
290 #define TRGMUX_3_GTM_019_016_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_019_016_SEL2_SHIFT)) & TRGMUX_3_GTM_019_016_SEL2_MASK)
291 
292 #define TRGMUX_3_GTM_019_016_SEL3_MASK           (0x7F000000U)
293 #define TRGMUX_3_GTM_019_016_SEL3_SHIFT          (24U)
294 #define TRGMUX_3_GTM_019_016_SEL3_WIDTH          (7U)
295 #define TRGMUX_3_GTM_019_016_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_019_016_SEL3_SHIFT)) & TRGMUX_3_GTM_019_016_SEL3_MASK)
296 
297 #define TRGMUX_3_GTM_019_016_LK_MASK             (0x80000000U)
298 #define TRGMUX_3_GTM_019_016_LK_SHIFT            (31U)
299 #define TRGMUX_3_GTM_019_016_LK_WIDTH            (1U)
300 #define TRGMUX_3_GTM_019_016_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_019_016_LK_SHIFT)) & TRGMUX_3_GTM_019_016_LK_MASK)
301 /*! @} */
302 
303 /*! @name GTM_023_020 - TRGMUX GTM_023_020 */
304 /*! @{ */
305 
306 #define TRGMUX_3_GTM_023_020_SEL0_MASK           (0x7FU)
307 #define TRGMUX_3_GTM_023_020_SEL0_SHIFT          (0U)
308 #define TRGMUX_3_GTM_023_020_SEL0_WIDTH          (7U)
309 #define TRGMUX_3_GTM_023_020_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_023_020_SEL0_SHIFT)) & TRGMUX_3_GTM_023_020_SEL0_MASK)
310 
311 #define TRGMUX_3_GTM_023_020_SEL1_MASK           (0x7F00U)
312 #define TRGMUX_3_GTM_023_020_SEL1_SHIFT          (8U)
313 #define TRGMUX_3_GTM_023_020_SEL1_WIDTH          (7U)
314 #define TRGMUX_3_GTM_023_020_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_023_020_SEL1_SHIFT)) & TRGMUX_3_GTM_023_020_SEL1_MASK)
315 
316 #define TRGMUX_3_GTM_023_020_SEL2_MASK           (0x7F0000U)
317 #define TRGMUX_3_GTM_023_020_SEL2_SHIFT          (16U)
318 #define TRGMUX_3_GTM_023_020_SEL2_WIDTH          (7U)
319 #define TRGMUX_3_GTM_023_020_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_023_020_SEL2_SHIFT)) & TRGMUX_3_GTM_023_020_SEL2_MASK)
320 
321 #define TRGMUX_3_GTM_023_020_SEL3_MASK           (0x7F000000U)
322 #define TRGMUX_3_GTM_023_020_SEL3_SHIFT          (24U)
323 #define TRGMUX_3_GTM_023_020_SEL3_WIDTH          (7U)
324 #define TRGMUX_3_GTM_023_020_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_023_020_SEL3_SHIFT)) & TRGMUX_3_GTM_023_020_SEL3_MASK)
325 
326 #define TRGMUX_3_GTM_023_020_LK_MASK             (0x80000000U)
327 #define TRGMUX_3_GTM_023_020_LK_SHIFT            (31U)
328 #define TRGMUX_3_GTM_023_020_LK_WIDTH            (1U)
329 #define TRGMUX_3_GTM_023_020_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_023_020_LK_SHIFT)) & TRGMUX_3_GTM_023_020_LK_MASK)
330 /*! @} */
331 
332 /*! @name GTM_027_024 - TRGMUX GTM_027_024 */
333 /*! @{ */
334 
335 #define TRGMUX_3_GTM_027_024_SEL0_MASK           (0x7FU)
336 #define TRGMUX_3_GTM_027_024_SEL0_SHIFT          (0U)
337 #define TRGMUX_3_GTM_027_024_SEL0_WIDTH          (7U)
338 #define TRGMUX_3_GTM_027_024_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_027_024_SEL0_SHIFT)) & TRGMUX_3_GTM_027_024_SEL0_MASK)
339 
340 #define TRGMUX_3_GTM_027_024_SEL1_MASK           (0x7F00U)
341 #define TRGMUX_3_GTM_027_024_SEL1_SHIFT          (8U)
342 #define TRGMUX_3_GTM_027_024_SEL1_WIDTH          (7U)
343 #define TRGMUX_3_GTM_027_024_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_027_024_SEL1_SHIFT)) & TRGMUX_3_GTM_027_024_SEL1_MASK)
344 
345 #define TRGMUX_3_GTM_027_024_SEL2_MASK           (0x7F0000U)
346 #define TRGMUX_3_GTM_027_024_SEL2_SHIFT          (16U)
347 #define TRGMUX_3_GTM_027_024_SEL2_WIDTH          (7U)
348 #define TRGMUX_3_GTM_027_024_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_027_024_SEL2_SHIFT)) & TRGMUX_3_GTM_027_024_SEL2_MASK)
349 
350 #define TRGMUX_3_GTM_027_024_SEL3_MASK           (0x7F000000U)
351 #define TRGMUX_3_GTM_027_024_SEL3_SHIFT          (24U)
352 #define TRGMUX_3_GTM_027_024_SEL3_WIDTH          (7U)
353 #define TRGMUX_3_GTM_027_024_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_027_024_SEL3_SHIFT)) & TRGMUX_3_GTM_027_024_SEL3_MASK)
354 
355 #define TRGMUX_3_GTM_027_024_LK_MASK             (0x80000000U)
356 #define TRGMUX_3_GTM_027_024_LK_SHIFT            (31U)
357 #define TRGMUX_3_GTM_027_024_LK_WIDTH            (1U)
358 #define TRGMUX_3_GTM_027_024_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_027_024_LK_SHIFT)) & TRGMUX_3_GTM_027_024_LK_MASK)
359 /*! @} */
360 
361 /*! @name GTM_031_028 - TRGMUX GTM_031_028 */
362 /*! @{ */
363 
364 #define TRGMUX_3_GTM_031_028_SEL0_MASK           (0x7FU)
365 #define TRGMUX_3_GTM_031_028_SEL0_SHIFT          (0U)
366 #define TRGMUX_3_GTM_031_028_SEL0_WIDTH          (7U)
367 #define TRGMUX_3_GTM_031_028_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_031_028_SEL0_SHIFT)) & TRGMUX_3_GTM_031_028_SEL0_MASK)
368 
369 #define TRGMUX_3_GTM_031_028_SEL1_MASK           (0x7F00U)
370 #define TRGMUX_3_GTM_031_028_SEL1_SHIFT          (8U)
371 #define TRGMUX_3_GTM_031_028_SEL1_WIDTH          (7U)
372 #define TRGMUX_3_GTM_031_028_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_031_028_SEL1_SHIFT)) & TRGMUX_3_GTM_031_028_SEL1_MASK)
373 
374 #define TRGMUX_3_GTM_031_028_SEL2_MASK           (0x7F0000U)
375 #define TRGMUX_3_GTM_031_028_SEL2_SHIFT          (16U)
376 #define TRGMUX_3_GTM_031_028_SEL2_WIDTH          (7U)
377 #define TRGMUX_3_GTM_031_028_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_031_028_SEL2_SHIFT)) & TRGMUX_3_GTM_031_028_SEL2_MASK)
378 
379 #define TRGMUX_3_GTM_031_028_SEL3_MASK           (0x7F000000U)
380 #define TRGMUX_3_GTM_031_028_SEL3_SHIFT          (24U)
381 #define TRGMUX_3_GTM_031_028_SEL3_WIDTH          (7U)
382 #define TRGMUX_3_GTM_031_028_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_031_028_SEL3_SHIFT)) & TRGMUX_3_GTM_031_028_SEL3_MASK)
383 
384 #define TRGMUX_3_GTM_031_028_LK_MASK             (0x80000000U)
385 #define TRGMUX_3_GTM_031_028_LK_SHIFT            (31U)
386 #define TRGMUX_3_GTM_031_028_LK_WIDTH            (1U)
387 #define TRGMUX_3_GTM_031_028_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_031_028_LK_SHIFT)) & TRGMUX_3_GTM_031_028_LK_MASK)
388 /*! @} */
389 
390 /*! @name GTM_035_032 - TRGMUX GTM_035_032 */
391 /*! @{ */
392 
393 #define TRGMUX_3_GTM_035_032_SEL0_MASK           (0x7FU)
394 #define TRGMUX_3_GTM_035_032_SEL0_SHIFT          (0U)
395 #define TRGMUX_3_GTM_035_032_SEL0_WIDTH          (7U)
396 #define TRGMUX_3_GTM_035_032_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_035_032_SEL0_SHIFT)) & TRGMUX_3_GTM_035_032_SEL0_MASK)
397 
398 #define TRGMUX_3_GTM_035_032_SEL1_MASK           (0x7F00U)
399 #define TRGMUX_3_GTM_035_032_SEL1_SHIFT          (8U)
400 #define TRGMUX_3_GTM_035_032_SEL1_WIDTH          (7U)
401 #define TRGMUX_3_GTM_035_032_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_035_032_SEL1_SHIFT)) & TRGMUX_3_GTM_035_032_SEL1_MASK)
402 
403 #define TRGMUX_3_GTM_035_032_SEL2_MASK           (0x7F0000U)
404 #define TRGMUX_3_GTM_035_032_SEL2_SHIFT          (16U)
405 #define TRGMUX_3_GTM_035_032_SEL2_WIDTH          (7U)
406 #define TRGMUX_3_GTM_035_032_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_035_032_SEL2_SHIFT)) & TRGMUX_3_GTM_035_032_SEL2_MASK)
407 
408 #define TRGMUX_3_GTM_035_032_SEL3_MASK           (0x7F000000U)
409 #define TRGMUX_3_GTM_035_032_SEL3_SHIFT          (24U)
410 #define TRGMUX_3_GTM_035_032_SEL3_WIDTH          (7U)
411 #define TRGMUX_3_GTM_035_032_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_035_032_SEL3_SHIFT)) & TRGMUX_3_GTM_035_032_SEL3_MASK)
412 
413 #define TRGMUX_3_GTM_035_032_LK_MASK             (0x80000000U)
414 #define TRGMUX_3_GTM_035_032_LK_SHIFT            (31U)
415 #define TRGMUX_3_GTM_035_032_LK_WIDTH            (1U)
416 #define TRGMUX_3_GTM_035_032_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_035_032_LK_SHIFT)) & TRGMUX_3_GTM_035_032_LK_MASK)
417 /*! @} */
418 
419 /*! @name GTM_039_036 - TRGMUX GTM_039_036 */
420 /*! @{ */
421 
422 #define TRGMUX_3_GTM_039_036_SEL0_MASK           (0x7FU)
423 #define TRGMUX_3_GTM_039_036_SEL0_SHIFT          (0U)
424 #define TRGMUX_3_GTM_039_036_SEL0_WIDTH          (7U)
425 #define TRGMUX_3_GTM_039_036_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_039_036_SEL0_SHIFT)) & TRGMUX_3_GTM_039_036_SEL0_MASK)
426 
427 #define TRGMUX_3_GTM_039_036_SEL1_MASK           (0x7F00U)
428 #define TRGMUX_3_GTM_039_036_SEL1_SHIFT          (8U)
429 #define TRGMUX_3_GTM_039_036_SEL1_WIDTH          (7U)
430 #define TRGMUX_3_GTM_039_036_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_039_036_SEL1_SHIFT)) & TRGMUX_3_GTM_039_036_SEL1_MASK)
431 
432 #define TRGMUX_3_GTM_039_036_SEL2_MASK           (0x7F0000U)
433 #define TRGMUX_3_GTM_039_036_SEL2_SHIFT          (16U)
434 #define TRGMUX_3_GTM_039_036_SEL2_WIDTH          (7U)
435 #define TRGMUX_3_GTM_039_036_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_039_036_SEL2_SHIFT)) & TRGMUX_3_GTM_039_036_SEL2_MASK)
436 
437 #define TRGMUX_3_GTM_039_036_SEL3_MASK           (0x7F000000U)
438 #define TRGMUX_3_GTM_039_036_SEL3_SHIFT          (24U)
439 #define TRGMUX_3_GTM_039_036_SEL3_WIDTH          (7U)
440 #define TRGMUX_3_GTM_039_036_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_039_036_SEL3_SHIFT)) & TRGMUX_3_GTM_039_036_SEL3_MASK)
441 
442 #define TRGMUX_3_GTM_039_036_LK_MASK             (0x80000000U)
443 #define TRGMUX_3_GTM_039_036_LK_SHIFT            (31U)
444 #define TRGMUX_3_GTM_039_036_LK_WIDTH            (1U)
445 #define TRGMUX_3_GTM_039_036_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_039_036_LK_SHIFT)) & TRGMUX_3_GTM_039_036_LK_MASK)
446 /*! @} */
447 
448 /*! @name GTM_043_040 - TRGMUX GTM_043_040 */
449 /*! @{ */
450 
451 #define TRGMUX_3_GTM_043_040_SEL0_MASK           (0x7FU)
452 #define TRGMUX_3_GTM_043_040_SEL0_SHIFT          (0U)
453 #define TRGMUX_3_GTM_043_040_SEL0_WIDTH          (7U)
454 #define TRGMUX_3_GTM_043_040_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_043_040_SEL0_SHIFT)) & TRGMUX_3_GTM_043_040_SEL0_MASK)
455 
456 #define TRGMUX_3_GTM_043_040_SEL1_MASK           (0x7F00U)
457 #define TRGMUX_3_GTM_043_040_SEL1_SHIFT          (8U)
458 #define TRGMUX_3_GTM_043_040_SEL1_WIDTH          (7U)
459 #define TRGMUX_3_GTM_043_040_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_043_040_SEL1_SHIFT)) & TRGMUX_3_GTM_043_040_SEL1_MASK)
460 
461 #define TRGMUX_3_GTM_043_040_SEL2_MASK           (0x7F0000U)
462 #define TRGMUX_3_GTM_043_040_SEL2_SHIFT          (16U)
463 #define TRGMUX_3_GTM_043_040_SEL2_WIDTH          (7U)
464 #define TRGMUX_3_GTM_043_040_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_043_040_SEL2_SHIFT)) & TRGMUX_3_GTM_043_040_SEL2_MASK)
465 
466 #define TRGMUX_3_GTM_043_040_SEL3_MASK           (0x7F000000U)
467 #define TRGMUX_3_GTM_043_040_SEL3_SHIFT          (24U)
468 #define TRGMUX_3_GTM_043_040_SEL3_WIDTH          (7U)
469 #define TRGMUX_3_GTM_043_040_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_043_040_SEL3_SHIFT)) & TRGMUX_3_GTM_043_040_SEL3_MASK)
470 
471 #define TRGMUX_3_GTM_043_040_LK_MASK             (0x80000000U)
472 #define TRGMUX_3_GTM_043_040_LK_SHIFT            (31U)
473 #define TRGMUX_3_GTM_043_040_LK_WIDTH            (1U)
474 #define TRGMUX_3_GTM_043_040_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_043_040_LK_SHIFT)) & TRGMUX_3_GTM_043_040_LK_MASK)
475 /*! @} */
476 
477 /*! @name GTM_047_044 - TRGMUX GTM_047_044 */
478 /*! @{ */
479 
480 #define TRGMUX_3_GTM_047_044_SEL0_MASK           (0x7FU)
481 #define TRGMUX_3_GTM_047_044_SEL0_SHIFT          (0U)
482 #define TRGMUX_3_GTM_047_044_SEL0_WIDTH          (7U)
483 #define TRGMUX_3_GTM_047_044_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_047_044_SEL0_SHIFT)) & TRGMUX_3_GTM_047_044_SEL0_MASK)
484 
485 #define TRGMUX_3_GTM_047_044_SEL1_MASK           (0x7F00U)
486 #define TRGMUX_3_GTM_047_044_SEL1_SHIFT          (8U)
487 #define TRGMUX_3_GTM_047_044_SEL1_WIDTH          (7U)
488 #define TRGMUX_3_GTM_047_044_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_047_044_SEL1_SHIFT)) & TRGMUX_3_GTM_047_044_SEL1_MASK)
489 
490 #define TRGMUX_3_GTM_047_044_SEL2_MASK           (0x7F0000U)
491 #define TRGMUX_3_GTM_047_044_SEL2_SHIFT          (16U)
492 #define TRGMUX_3_GTM_047_044_SEL2_WIDTH          (7U)
493 #define TRGMUX_3_GTM_047_044_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_047_044_SEL2_SHIFT)) & TRGMUX_3_GTM_047_044_SEL2_MASK)
494 
495 #define TRGMUX_3_GTM_047_044_SEL3_MASK           (0x7F000000U)
496 #define TRGMUX_3_GTM_047_044_SEL3_SHIFT          (24U)
497 #define TRGMUX_3_GTM_047_044_SEL3_WIDTH          (7U)
498 #define TRGMUX_3_GTM_047_044_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_047_044_SEL3_SHIFT)) & TRGMUX_3_GTM_047_044_SEL3_MASK)
499 
500 #define TRGMUX_3_GTM_047_044_LK_MASK             (0x80000000U)
501 #define TRGMUX_3_GTM_047_044_LK_SHIFT            (31U)
502 #define TRGMUX_3_GTM_047_044_LK_WIDTH            (1U)
503 #define TRGMUX_3_GTM_047_044_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_047_044_LK_SHIFT)) & TRGMUX_3_GTM_047_044_LK_MASK)
504 /*! @} */
505 
506 /*! @name GTM_051_048 - TRGMUX GTM_051_048 */
507 /*! @{ */
508 
509 #define TRGMUX_3_GTM_051_048_SEL0_MASK           (0x7FU)
510 #define TRGMUX_3_GTM_051_048_SEL0_SHIFT          (0U)
511 #define TRGMUX_3_GTM_051_048_SEL0_WIDTH          (7U)
512 #define TRGMUX_3_GTM_051_048_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_051_048_SEL0_SHIFT)) & TRGMUX_3_GTM_051_048_SEL0_MASK)
513 
514 #define TRGMUX_3_GTM_051_048_SEL1_MASK           (0x7F00U)
515 #define TRGMUX_3_GTM_051_048_SEL1_SHIFT          (8U)
516 #define TRGMUX_3_GTM_051_048_SEL1_WIDTH          (7U)
517 #define TRGMUX_3_GTM_051_048_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_051_048_SEL1_SHIFT)) & TRGMUX_3_GTM_051_048_SEL1_MASK)
518 
519 #define TRGMUX_3_GTM_051_048_SEL2_MASK           (0x7F0000U)
520 #define TRGMUX_3_GTM_051_048_SEL2_SHIFT          (16U)
521 #define TRGMUX_3_GTM_051_048_SEL2_WIDTH          (7U)
522 #define TRGMUX_3_GTM_051_048_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_051_048_SEL2_SHIFT)) & TRGMUX_3_GTM_051_048_SEL2_MASK)
523 
524 #define TRGMUX_3_GTM_051_048_SEL3_MASK           (0x7F000000U)
525 #define TRGMUX_3_GTM_051_048_SEL3_SHIFT          (24U)
526 #define TRGMUX_3_GTM_051_048_SEL3_WIDTH          (7U)
527 #define TRGMUX_3_GTM_051_048_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_051_048_SEL3_SHIFT)) & TRGMUX_3_GTM_051_048_SEL3_MASK)
528 
529 #define TRGMUX_3_GTM_051_048_LK_MASK             (0x80000000U)
530 #define TRGMUX_3_GTM_051_048_LK_SHIFT            (31U)
531 #define TRGMUX_3_GTM_051_048_LK_WIDTH            (1U)
532 #define TRGMUX_3_GTM_051_048_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_051_048_LK_SHIFT)) & TRGMUX_3_GTM_051_048_LK_MASK)
533 /*! @} */
534 
535 /*! @name GTM_055_052 - TRGMUX GTM_055_052 */
536 /*! @{ */
537 
538 #define TRGMUX_3_GTM_055_052_SEL0_MASK           (0x7FU)
539 #define TRGMUX_3_GTM_055_052_SEL0_SHIFT          (0U)
540 #define TRGMUX_3_GTM_055_052_SEL0_WIDTH          (7U)
541 #define TRGMUX_3_GTM_055_052_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_055_052_SEL0_SHIFT)) & TRGMUX_3_GTM_055_052_SEL0_MASK)
542 
543 #define TRGMUX_3_GTM_055_052_SEL1_MASK           (0x7F00U)
544 #define TRGMUX_3_GTM_055_052_SEL1_SHIFT          (8U)
545 #define TRGMUX_3_GTM_055_052_SEL1_WIDTH          (7U)
546 #define TRGMUX_3_GTM_055_052_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_055_052_SEL1_SHIFT)) & TRGMUX_3_GTM_055_052_SEL1_MASK)
547 
548 #define TRGMUX_3_GTM_055_052_SEL2_MASK           (0x7F0000U)
549 #define TRGMUX_3_GTM_055_052_SEL2_SHIFT          (16U)
550 #define TRGMUX_3_GTM_055_052_SEL2_WIDTH          (7U)
551 #define TRGMUX_3_GTM_055_052_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_055_052_SEL2_SHIFT)) & TRGMUX_3_GTM_055_052_SEL2_MASK)
552 
553 #define TRGMUX_3_GTM_055_052_SEL3_MASK           (0x7F000000U)
554 #define TRGMUX_3_GTM_055_052_SEL3_SHIFT          (24U)
555 #define TRGMUX_3_GTM_055_052_SEL3_WIDTH          (7U)
556 #define TRGMUX_3_GTM_055_052_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_055_052_SEL3_SHIFT)) & TRGMUX_3_GTM_055_052_SEL3_MASK)
557 
558 #define TRGMUX_3_GTM_055_052_LK_MASK             (0x80000000U)
559 #define TRGMUX_3_GTM_055_052_LK_SHIFT            (31U)
560 #define TRGMUX_3_GTM_055_052_LK_WIDTH            (1U)
561 #define TRGMUX_3_GTM_055_052_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_055_052_LK_SHIFT)) & TRGMUX_3_GTM_055_052_LK_MASK)
562 /*! @} */
563 
564 /*! @name GTM_059_056 - TRGMUX GTM_059_056 */
565 /*! @{ */
566 
567 #define TRGMUX_3_GTM_059_056_SEL0_MASK           (0x7FU)
568 #define TRGMUX_3_GTM_059_056_SEL0_SHIFT          (0U)
569 #define TRGMUX_3_GTM_059_056_SEL0_WIDTH          (7U)
570 #define TRGMUX_3_GTM_059_056_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_059_056_SEL0_SHIFT)) & TRGMUX_3_GTM_059_056_SEL0_MASK)
571 
572 #define TRGMUX_3_GTM_059_056_SEL1_MASK           (0x7F00U)
573 #define TRGMUX_3_GTM_059_056_SEL1_SHIFT          (8U)
574 #define TRGMUX_3_GTM_059_056_SEL1_WIDTH          (7U)
575 #define TRGMUX_3_GTM_059_056_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_059_056_SEL1_SHIFT)) & TRGMUX_3_GTM_059_056_SEL1_MASK)
576 
577 #define TRGMUX_3_GTM_059_056_SEL2_MASK           (0x7F0000U)
578 #define TRGMUX_3_GTM_059_056_SEL2_SHIFT          (16U)
579 #define TRGMUX_3_GTM_059_056_SEL2_WIDTH          (7U)
580 #define TRGMUX_3_GTM_059_056_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_059_056_SEL2_SHIFT)) & TRGMUX_3_GTM_059_056_SEL2_MASK)
581 
582 #define TRGMUX_3_GTM_059_056_SEL3_MASK           (0x7F000000U)
583 #define TRGMUX_3_GTM_059_056_SEL3_SHIFT          (24U)
584 #define TRGMUX_3_GTM_059_056_SEL3_WIDTH          (7U)
585 #define TRGMUX_3_GTM_059_056_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_059_056_SEL3_SHIFT)) & TRGMUX_3_GTM_059_056_SEL3_MASK)
586 
587 #define TRGMUX_3_GTM_059_056_LK_MASK             (0x80000000U)
588 #define TRGMUX_3_GTM_059_056_LK_SHIFT            (31U)
589 #define TRGMUX_3_GTM_059_056_LK_WIDTH            (1U)
590 #define TRGMUX_3_GTM_059_056_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_059_056_LK_SHIFT)) & TRGMUX_3_GTM_059_056_LK_MASK)
591 /*! @} */
592 
593 /*! @name GTM_063_060 - TRGMUX GTM_063_060 */
594 /*! @{ */
595 
596 #define TRGMUX_3_GTM_063_060_SEL0_MASK           (0x7FU)
597 #define TRGMUX_3_GTM_063_060_SEL0_SHIFT          (0U)
598 #define TRGMUX_3_GTM_063_060_SEL0_WIDTH          (7U)
599 #define TRGMUX_3_GTM_063_060_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_063_060_SEL0_SHIFT)) & TRGMUX_3_GTM_063_060_SEL0_MASK)
600 
601 #define TRGMUX_3_GTM_063_060_SEL1_MASK           (0x7F00U)
602 #define TRGMUX_3_GTM_063_060_SEL1_SHIFT          (8U)
603 #define TRGMUX_3_GTM_063_060_SEL1_WIDTH          (7U)
604 #define TRGMUX_3_GTM_063_060_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_063_060_SEL1_SHIFT)) & TRGMUX_3_GTM_063_060_SEL1_MASK)
605 
606 #define TRGMUX_3_GTM_063_060_SEL2_MASK           (0x7F0000U)
607 #define TRGMUX_3_GTM_063_060_SEL2_SHIFT          (16U)
608 #define TRGMUX_3_GTM_063_060_SEL2_WIDTH          (7U)
609 #define TRGMUX_3_GTM_063_060_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_063_060_SEL2_SHIFT)) & TRGMUX_3_GTM_063_060_SEL2_MASK)
610 
611 #define TRGMUX_3_GTM_063_060_SEL3_MASK           (0x7F000000U)
612 #define TRGMUX_3_GTM_063_060_SEL3_SHIFT          (24U)
613 #define TRGMUX_3_GTM_063_060_SEL3_WIDTH          (7U)
614 #define TRGMUX_3_GTM_063_060_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_063_060_SEL3_SHIFT)) & TRGMUX_3_GTM_063_060_SEL3_MASK)
615 
616 #define TRGMUX_3_GTM_063_060_LK_MASK             (0x80000000U)
617 #define TRGMUX_3_GTM_063_060_LK_SHIFT            (31U)
618 #define TRGMUX_3_GTM_063_060_LK_WIDTH            (1U)
619 #define TRGMUX_3_GTM_063_060_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_063_060_LK_SHIFT)) & TRGMUX_3_GTM_063_060_LK_MASK)
620 /*! @} */
621 
622 /*! @name GTM_067_064 - TRGMUX GTM_067_064 */
623 /*! @{ */
624 
625 #define TRGMUX_3_GTM_067_064_SEL0_MASK           (0x7FU)
626 #define TRGMUX_3_GTM_067_064_SEL0_SHIFT          (0U)
627 #define TRGMUX_3_GTM_067_064_SEL0_WIDTH          (7U)
628 #define TRGMUX_3_GTM_067_064_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_067_064_SEL0_SHIFT)) & TRGMUX_3_GTM_067_064_SEL0_MASK)
629 
630 #define TRGMUX_3_GTM_067_064_SEL1_MASK           (0x7F00U)
631 #define TRGMUX_3_GTM_067_064_SEL1_SHIFT          (8U)
632 #define TRGMUX_3_GTM_067_064_SEL1_WIDTH          (7U)
633 #define TRGMUX_3_GTM_067_064_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_067_064_SEL1_SHIFT)) & TRGMUX_3_GTM_067_064_SEL1_MASK)
634 
635 #define TRGMUX_3_GTM_067_064_SEL2_MASK           (0x7F0000U)
636 #define TRGMUX_3_GTM_067_064_SEL2_SHIFT          (16U)
637 #define TRGMUX_3_GTM_067_064_SEL2_WIDTH          (7U)
638 #define TRGMUX_3_GTM_067_064_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_067_064_SEL2_SHIFT)) & TRGMUX_3_GTM_067_064_SEL2_MASK)
639 
640 #define TRGMUX_3_GTM_067_064_SEL3_MASK           (0x7F000000U)
641 #define TRGMUX_3_GTM_067_064_SEL3_SHIFT          (24U)
642 #define TRGMUX_3_GTM_067_064_SEL3_WIDTH          (7U)
643 #define TRGMUX_3_GTM_067_064_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_067_064_SEL3_SHIFT)) & TRGMUX_3_GTM_067_064_SEL3_MASK)
644 
645 #define TRGMUX_3_GTM_067_064_LK_MASK             (0x80000000U)
646 #define TRGMUX_3_GTM_067_064_LK_SHIFT            (31U)
647 #define TRGMUX_3_GTM_067_064_LK_WIDTH            (1U)
648 #define TRGMUX_3_GTM_067_064_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_067_064_LK_SHIFT)) & TRGMUX_3_GTM_067_064_LK_MASK)
649 /*! @} */
650 
651 /*! @name GTM_071_068 - TRGMUX GTM_071_068 */
652 /*! @{ */
653 
654 #define TRGMUX_3_GTM_071_068_SEL0_MASK           (0x7FU)
655 #define TRGMUX_3_GTM_071_068_SEL0_SHIFT          (0U)
656 #define TRGMUX_3_GTM_071_068_SEL0_WIDTH          (7U)
657 #define TRGMUX_3_GTM_071_068_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_071_068_SEL0_SHIFT)) & TRGMUX_3_GTM_071_068_SEL0_MASK)
658 
659 #define TRGMUX_3_GTM_071_068_SEL1_MASK           (0x7F00U)
660 #define TRGMUX_3_GTM_071_068_SEL1_SHIFT          (8U)
661 #define TRGMUX_3_GTM_071_068_SEL1_WIDTH          (7U)
662 #define TRGMUX_3_GTM_071_068_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_071_068_SEL1_SHIFT)) & TRGMUX_3_GTM_071_068_SEL1_MASK)
663 
664 #define TRGMUX_3_GTM_071_068_SEL2_MASK           (0x7F0000U)
665 #define TRGMUX_3_GTM_071_068_SEL2_SHIFT          (16U)
666 #define TRGMUX_3_GTM_071_068_SEL2_WIDTH          (7U)
667 #define TRGMUX_3_GTM_071_068_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_071_068_SEL2_SHIFT)) & TRGMUX_3_GTM_071_068_SEL2_MASK)
668 
669 #define TRGMUX_3_GTM_071_068_SEL3_MASK           (0x7F000000U)
670 #define TRGMUX_3_GTM_071_068_SEL3_SHIFT          (24U)
671 #define TRGMUX_3_GTM_071_068_SEL3_WIDTH          (7U)
672 #define TRGMUX_3_GTM_071_068_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_071_068_SEL3_SHIFT)) & TRGMUX_3_GTM_071_068_SEL3_MASK)
673 
674 #define TRGMUX_3_GTM_071_068_LK_MASK             (0x80000000U)
675 #define TRGMUX_3_GTM_071_068_LK_SHIFT            (31U)
676 #define TRGMUX_3_GTM_071_068_LK_WIDTH            (1U)
677 #define TRGMUX_3_GTM_071_068_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_071_068_LK_SHIFT)) & TRGMUX_3_GTM_071_068_LK_MASK)
678 /*! @} */
679 
680 /*! @name GTM_075_072 - TRGMUX GTM_075_072 */
681 /*! @{ */
682 
683 #define TRGMUX_3_GTM_075_072_SEL0_MASK           (0x7FU)
684 #define TRGMUX_3_GTM_075_072_SEL0_SHIFT          (0U)
685 #define TRGMUX_3_GTM_075_072_SEL0_WIDTH          (7U)
686 #define TRGMUX_3_GTM_075_072_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_075_072_SEL0_SHIFT)) & TRGMUX_3_GTM_075_072_SEL0_MASK)
687 
688 #define TRGMUX_3_GTM_075_072_SEL1_MASK           (0x7F00U)
689 #define TRGMUX_3_GTM_075_072_SEL1_SHIFT          (8U)
690 #define TRGMUX_3_GTM_075_072_SEL1_WIDTH          (7U)
691 #define TRGMUX_3_GTM_075_072_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_075_072_SEL1_SHIFT)) & TRGMUX_3_GTM_075_072_SEL1_MASK)
692 
693 #define TRGMUX_3_GTM_075_072_SEL2_MASK           (0x7F0000U)
694 #define TRGMUX_3_GTM_075_072_SEL2_SHIFT          (16U)
695 #define TRGMUX_3_GTM_075_072_SEL2_WIDTH          (7U)
696 #define TRGMUX_3_GTM_075_072_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_075_072_SEL2_SHIFT)) & TRGMUX_3_GTM_075_072_SEL2_MASK)
697 
698 #define TRGMUX_3_GTM_075_072_SEL3_MASK           (0x7F000000U)
699 #define TRGMUX_3_GTM_075_072_SEL3_SHIFT          (24U)
700 #define TRGMUX_3_GTM_075_072_SEL3_WIDTH          (7U)
701 #define TRGMUX_3_GTM_075_072_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_075_072_SEL3_SHIFT)) & TRGMUX_3_GTM_075_072_SEL3_MASK)
702 
703 #define TRGMUX_3_GTM_075_072_LK_MASK             (0x80000000U)
704 #define TRGMUX_3_GTM_075_072_LK_SHIFT            (31U)
705 #define TRGMUX_3_GTM_075_072_LK_WIDTH            (1U)
706 #define TRGMUX_3_GTM_075_072_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_075_072_LK_SHIFT)) & TRGMUX_3_GTM_075_072_LK_MASK)
707 /*! @} */
708 
709 /*! @name GTM_079_076 - TRGMUX GTM_079_076 */
710 /*! @{ */
711 
712 #define TRGMUX_3_GTM_079_076_SEL0_MASK           (0x7FU)
713 #define TRGMUX_3_GTM_079_076_SEL0_SHIFT          (0U)
714 #define TRGMUX_3_GTM_079_076_SEL0_WIDTH          (7U)
715 #define TRGMUX_3_GTM_079_076_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_079_076_SEL0_SHIFT)) & TRGMUX_3_GTM_079_076_SEL0_MASK)
716 
717 #define TRGMUX_3_GTM_079_076_SEL1_MASK           (0x7F00U)
718 #define TRGMUX_3_GTM_079_076_SEL1_SHIFT          (8U)
719 #define TRGMUX_3_GTM_079_076_SEL1_WIDTH          (7U)
720 #define TRGMUX_3_GTM_079_076_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_079_076_SEL1_SHIFT)) & TRGMUX_3_GTM_079_076_SEL1_MASK)
721 
722 #define TRGMUX_3_GTM_079_076_SEL2_MASK           (0x7F0000U)
723 #define TRGMUX_3_GTM_079_076_SEL2_SHIFT          (16U)
724 #define TRGMUX_3_GTM_079_076_SEL2_WIDTH          (7U)
725 #define TRGMUX_3_GTM_079_076_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_079_076_SEL2_SHIFT)) & TRGMUX_3_GTM_079_076_SEL2_MASK)
726 
727 #define TRGMUX_3_GTM_079_076_SEL3_MASK           (0x7F000000U)
728 #define TRGMUX_3_GTM_079_076_SEL3_SHIFT          (24U)
729 #define TRGMUX_3_GTM_079_076_SEL3_WIDTH          (7U)
730 #define TRGMUX_3_GTM_079_076_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_079_076_SEL3_SHIFT)) & TRGMUX_3_GTM_079_076_SEL3_MASK)
731 
732 #define TRGMUX_3_GTM_079_076_LK_MASK             (0x80000000U)
733 #define TRGMUX_3_GTM_079_076_LK_SHIFT            (31U)
734 #define TRGMUX_3_GTM_079_076_LK_WIDTH            (1U)
735 #define TRGMUX_3_GTM_079_076_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_079_076_LK_SHIFT)) & TRGMUX_3_GTM_079_076_LK_MASK)
736 /*! @} */
737 
738 /*! @name GTM_083_080 - TRGMUX GTM_083_080 */
739 /*! @{ */
740 
741 #define TRGMUX_3_GTM_083_080_SEL0_MASK           (0x7FU)
742 #define TRGMUX_3_GTM_083_080_SEL0_SHIFT          (0U)
743 #define TRGMUX_3_GTM_083_080_SEL0_WIDTH          (7U)
744 #define TRGMUX_3_GTM_083_080_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_083_080_SEL0_SHIFT)) & TRGMUX_3_GTM_083_080_SEL0_MASK)
745 
746 #define TRGMUX_3_GTM_083_080_SEL1_MASK           (0x7F00U)
747 #define TRGMUX_3_GTM_083_080_SEL1_SHIFT          (8U)
748 #define TRGMUX_3_GTM_083_080_SEL1_WIDTH          (7U)
749 #define TRGMUX_3_GTM_083_080_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_083_080_SEL1_SHIFT)) & TRGMUX_3_GTM_083_080_SEL1_MASK)
750 
751 #define TRGMUX_3_GTM_083_080_SEL2_MASK           (0x7F0000U)
752 #define TRGMUX_3_GTM_083_080_SEL2_SHIFT          (16U)
753 #define TRGMUX_3_GTM_083_080_SEL2_WIDTH          (7U)
754 #define TRGMUX_3_GTM_083_080_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_083_080_SEL2_SHIFT)) & TRGMUX_3_GTM_083_080_SEL2_MASK)
755 
756 #define TRGMUX_3_GTM_083_080_SEL3_MASK           (0x7F000000U)
757 #define TRGMUX_3_GTM_083_080_SEL3_SHIFT          (24U)
758 #define TRGMUX_3_GTM_083_080_SEL3_WIDTH          (7U)
759 #define TRGMUX_3_GTM_083_080_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_083_080_SEL3_SHIFT)) & TRGMUX_3_GTM_083_080_SEL3_MASK)
760 
761 #define TRGMUX_3_GTM_083_080_LK_MASK             (0x80000000U)
762 #define TRGMUX_3_GTM_083_080_LK_SHIFT            (31U)
763 #define TRGMUX_3_GTM_083_080_LK_WIDTH            (1U)
764 #define TRGMUX_3_GTM_083_080_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_083_080_LK_SHIFT)) & TRGMUX_3_GTM_083_080_LK_MASK)
765 /*! @} */
766 
767 /*! @name GTM_087_084 - TRGMUX GTM_087_084 */
768 /*! @{ */
769 
770 #define TRGMUX_3_GTM_087_084_SEL0_MASK           (0x7FU)
771 #define TRGMUX_3_GTM_087_084_SEL0_SHIFT          (0U)
772 #define TRGMUX_3_GTM_087_084_SEL0_WIDTH          (7U)
773 #define TRGMUX_3_GTM_087_084_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_087_084_SEL0_SHIFT)) & TRGMUX_3_GTM_087_084_SEL0_MASK)
774 
775 #define TRGMUX_3_GTM_087_084_SEL1_MASK           (0x7F00U)
776 #define TRGMUX_3_GTM_087_084_SEL1_SHIFT          (8U)
777 #define TRGMUX_3_GTM_087_084_SEL1_WIDTH          (7U)
778 #define TRGMUX_3_GTM_087_084_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_087_084_SEL1_SHIFT)) & TRGMUX_3_GTM_087_084_SEL1_MASK)
779 
780 #define TRGMUX_3_GTM_087_084_SEL2_MASK           (0x7F0000U)
781 #define TRGMUX_3_GTM_087_084_SEL2_SHIFT          (16U)
782 #define TRGMUX_3_GTM_087_084_SEL2_WIDTH          (7U)
783 #define TRGMUX_3_GTM_087_084_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_087_084_SEL2_SHIFT)) & TRGMUX_3_GTM_087_084_SEL2_MASK)
784 
785 #define TRGMUX_3_GTM_087_084_SEL3_MASK           (0x7F000000U)
786 #define TRGMUX_3_GTM_087_084_SEL3_SHIFT          (24U)
787 #define TRGMUX_3_GTM_087_084_SEL3_WIDTH          (7U)
788 #define TRGMUX_3_GTM_087_084_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_087_084_SEL3_SHIFT)) & TRGMUX_3_GTM_087_084_SEL3_MASK)
789 
790 #define TRGMUX_3_GTM_087_084_LK_MASK             (0x80000000U)
791 #define TRGMUX_3_GTM_087_084_LK_SHIFT            (31U)
792 #define TRGMUX_3_GTM_087_084_LK_WIDTH            (1U)
793 #define TRGMUX_3_GTM_087_084_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_087_084_LK_SHIFT)) & TRGMUX_3_GTM_087_084_LK_MASK)
794 /*! @} */
795 
796 /*! @name GTM_091_088 - TRGMUX GTM_091_088 */
797 /*! @{ */
798 
799 #define TRGMUX_3_GTM_091_088_SEL0_MASK           (0x7FU)
800 #define TRGMUX_3_GTM_091_088_SEL0_SHIFT          (0U)
801 #define TRGMUX_3_GTM_091_088_SEL0_WIDTH          (7U)
802 #define TRGMUX_3_GTM_091_088_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_091_088_SEL0_SHIFT)) & TRGMUX_3_GTM_091_088_SEL0_MASK)
803 
804 #define TRGMUX_3_GTM_091_088_SEL1_MASK           (0x7F00U)
805 #define TRGMUX_3_GTM_091_088_SEL1_SHIFT          (8U)
806 #define TRGMUX_3_GTM_091_088_SEL1_WIDTH          (7U)
807 #define TRGMUX_3_GTM_091_088_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_091_088_SEL1_SHIFT)) & TRGMUX_3_GTM_091_088_SEL1_MASK)
808 
809 #define TRGMUX_3_GTM_091_088_SEL2_MASK           (0x7F0000U)
810 #define TRGMUX_3_GTM_091_088_SEL2_SHIFT          (16U)
811 #define TRGMUX_3_GTM_091_088_SEL2_WIDTH          (7U)
812 #define TRGMUX_3_GTM_091_088_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_091_088_SEL2_SHIFT)) & TRGMUX_3_GTM_091_088_SEL2_MASK)
813 
814 #define TRGMUX_3_GTM_091_088_SEL3_MASK           (0x7F000000U)
815 #define TRGMUX_3_GTM_091_088_SEL3_SHIFT          (24U)
816 #define TRGMUX_3_GTM_091_088_SEL3_WIDTH          (7U)
817 #define TRGMUX_3_GTM_091_088_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_091_088_SEL3_SHIFT)) & TRGMUX_3_GTM_091_088_SEL3_MASK)
818 
819 #define TRGMUX_3_GTM_091_088_LK_MASK             (0x80000000U)
820 #define TRGMUX_3_GTM_091_088_LK_SHIFT            (31U)
821 #define TRGMUX_3_GTM_091_088_LK_WIDTH            (1U)
822 #define TRGMUX_3_GTM_091_088_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_091_088_LK_SHIFT)) & TRGMUX_3_GTM_091_088_LK_MASK)
823 /*! @} */
824 
825 /*! @name GTM_095_092 - TRGMUX GTM_095_092 */
826 /*! @{ */
827 
828 #define TRGMUX_3_GTM_095_092_SEL0_MASK           (0x7FU)
829 #define TRGMUX_3_GTM_095_092_SEL0_SHIFT          (0U)
830 #define TRGMUX_3_GTM_095_092_SEL0_WIDTH          (7U)
831 #define TRGMUX_3_GTM_095_092_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_095_092_SEL0_SHIFT)) & TRGMUX_3_GTM_095_092_SEL0_MASK)
832 
833 #define TRGMUX_3_GTM_095_092_SEL1_MASK           (0x7F00U)
834 #define TRGMUX_3_GTM_095_092_SEL1_SHIFT          (8U)
835 #define TRGMUX_3_GTM_095_092_SEL1_WIDTH          (7U)
836 #define TRGMUX_3_GTM_095_092_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_095_092_SEL1_SHIFT)) & TRGMUX_3_GTM_095_092_SEL1_MASK)
837 
838 #define TRGMUX_3_GTM_095_092_SEL2_MASK           (0x7F0000U)
839 #define TRGMUX_3_GTM_095_092_SEL2_SHIFT          (16U)
840 #define TRGMUX_3_GTM_095_092_SEL2_WIDTH          (7U)
841 #define TRGMUX_3_GTM_095_092_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_095_092_SEL2_SHIFT)) & TRGMUX_3_GTM_095_092_SEL2_MASK)
842 
843 #define TRGMUX_3_GTM_095_092_SEL3_MASK           (0x7F000000U)
844 #define TRGMUX_3_GTM_095_092_SEL3_SHIFT          (24U)
845 #define TRGMUX_3_GTM_095_092_SEL3_WIDTH          (7U)
846 #define TRGMUX_3_GTM_095_092_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_095_092_SEL3_SHIFT)) & TRGMUX_3_GTM_095_092_SEL3_MASK)
847 
848 #define TRGMUX_3_GTM_095_092_LK_MASK             (0x80000000U)
849 #define TRGMUX_3_GTM_095_092_LK_SHIFT            (31U)
850 #define TRGMUX_3_GTM_095_092_LK_WIDTH            (1U)
851 #define TRGMUX_3_GTM_095_092_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_095_092_LK_SHIFT)) & TRGMUX_3_GTM_095_092_LK_MASK)
852 /*! @} */
853 
854 /*! @name GTM_099_096 - TRGMUX GTM_099_096 */
855 /*! @{ */
856 
857 #define TRGMUX_3_GTM_099_096_SEL0_MASK           (0x7FU)
858 #define TRGMUX_3_GTM_099_096_SEL0_SHIFT          (0U)
859 #define TRGMUX_3_GTM_099_096_SEL0_WIDTH          (7U)
860 #define TRGMUX_3_GTM_099_096_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_099_096_SEL0_SHIFT)) & TRGMUX_3_GTM_099_096_SEL0_MASK)
861 
862 #define TRGMUX_3_GTM_099_096_SEL1_MASK           (0x7F00U)
863 #define TRGMUX_3_GTM_099_096_SEL1_SHIFT          (8U)
864 #define TRGMUX_3_GTM_099_096_SEL1_WIDTH          (7U)
865 #define TRGMUX_3_GTM_099_096_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_099_096_SEL1_SHIFT)) & TRGMUX_3_GTM_099_096_SEL1_MASK)
866 
867 #define TRGMUX_3_GTM_099_096_SEL2_MASK           (0x7F0000U)
868 #define TRGMUX_3_GTM_099_096_SEL2_SHIFT          (16U)
869 #define TRGMUX_3_GTM_099_096_SEL2_WIDTH          (7U)
870 #define TRGMUX_3_GTM_099_096_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_099_096_SEL2_SHIFT)) & TRGMUX_3_GTM_099_096_SEL2_MASK)
871 
872 #define TRGMUX_3_GTM_099_096_SEL3_MASK           (0x7F000000U)
873 #define TRGMUX_3_GTM_099_096_SEL3_SHIFT          (24U)
874 #define TRGMUX_3_GTM_099_096_SEL3_WIDTH          (7U)
875 #define TRGMUX_3_GTM_099_096_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_099_096_SEL3_SHIFT)) & TRGMUX_3_GTM_099_096_SEL3_MASK)
876 
877 #define TRGMUX_3_GTM_099_096_LK_MASK             (0x80000000U)
878 #define TRGMUX_3_GTM_099_096_LK_SHIFT            (31U)
879 #define TRGMUX_3_GTM_099_096_LK_WIDTH            (1U)
880 #define TRGMUX_3_GTM_099_096_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_099_096_LK_SHIFT)) & TRGMUX_3_GTM_099_096_LK_MASK)
881 /*! @} */
882 
883 /*! @name GTM_103_100 - TRGMUX GTM_103_100 */
884 /*! @{ */
885 
886 #define TRGMUX_3_GTM_103_100_SEL0_MASK           (0x7FU)
887 #define TRGMUX_3_GTM_103_100_SEL0_SHIFT          (0U)
888 #define TRGMUX_3_GTM_103_100_SEL0_WIDTH          (7U)
889 #define TRGMUX_3_GTM_103_100_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_103_100_SEL0_SHIFT)) & TRGMUX_3_GTM_103_100_SEL0_MASK)
890 
891 #define TRGMUX_3_GTM_103_100_SEL1_MASK           (0x7F00U)
892 #define TRGMUX_3_GTM_103_100_SEL1_SHIFT          (8U)
893 #define TRGMUX_3_GTM_103_100_SEL1_WIDTH          (7U)
894 #define TRGMUX_3_GTM_103_100_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_103_100_SEL1_SHIFT)) & TRGMUX_3_GTM_103_100_SEL1_MASK)
895 
896 #define TRGMUX_3_GTM_103_100_SEL2_MASK           (0x7F0000U)
897 #define TRGMUX_3_GTM_103_100_SEL2_SHIFT          (16U)
898 #define TRGMUX_3_GTM_103_100_SEL2_WIDTH          (7U)
899 #define TRGMUX_3_GTM_103_100_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_103_100_SEL2_SHIFT)) & TRGMUX_3_GTM_103_100_SEL2_MASK)
900 
901 #define TRGMUX_3_GTM_103_100_SEL3_MASK           (0x7F000000U)
902 #define TRGMUX_3_GTM_103_100_SEL3_SHIFT          (24U)
903 #define TRGMUX_3_GTM_103_100_SEL3_WIDTH          (7U)
904 #define TRGMUX_3_GTM_103_100_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_103_100_SEL3_SHIFT)) & TRGMUX_3_GTM_103_100_SEL3_MASK)
905 
906 #define TRGMUX_3_GTM_103_100_LK_MASK             (0x80000000U)
907 #define TRGMUX_3_GTM_103_100_LK_SHIFT            (31U)
908 #define TRGMUX_3_GTM_103_100_LK_WIDTH            (1U)
909 #define TRGMUX_3_GTM_103_100_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_103_100_LK_SHIFT)) & TRGMUX_3_GTM_103_100_LK_MASK)
910 /*! @} */
911 
912 /*! @name GTM_107_104 - TRGMUX GTM_107_104 */
913 /*! @{ */
914 
915 #define TRGMUX_3_GTM_107_104_SEL0_MASK           (0x7FU)
916 #define TRGMUX_3_GTM_107_104_SEL0_SHIFT          (0U)
917 #define TRGMUX_3_GTM_107_104_SEL0_WIDTH          (7U)
918 #define TRGMUX_3_GTM_107_104_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_107_104_SEL0_SHIFT)) & TRGMUX_3_GTM_107_104_SEL0_MASK)
919 
920 #define TRGMUX_3_GTM_107_104_SEL1_MASK           (0x7F00U)
921 #define TRGMUX_3_GTM_107_104_SEL1_SHIFT          (8U)
922 #define TRGMUX_3_GTM_107_104_SEL1_WIDTH          (7U)
923 #define TRGMUX_3_GTM_107_104_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_107_104_SEL1_SHIFT)) & TRGMUX_3_GTM_107_104_SEL1_MASK)
924 
925 #define TRGMUX_3_GTM_107_104_SEL2_MASK           (0x7F0000U)
926 #define TRGMUX_3_GTM_107_104_SEL2_SHIFT          (16U)
927 #define TRGMUX_3_GTM_107_104_SEL2_WIDTH          (7U)
928 #define TRGMUX_3_GTM_107_104_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_107_104_SEL2_SHIFT)) & TRGMUX_3_GTM_107_104_SEL2_MASK)
929 
930 #define TRGMUX_3_GTM_107_104_SEL3_MASK           (0x7F000000U)
931 #define TRGMUX_3_GTM_107_104_SEL3_SHIFT          (24U)
932 #define TRGMUX_3_GTM_107_104_SEL3_WIDTH          (7U)
933 #define TRGMUX_3_GTM_107_104_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_107_104_SEL3_SHIFT)) & TRGMUX_3_GTM_107_104_SEL3_MASK)
934 
935 #define TRGMUX_3_GTM_107_104_LK_MASK             (0x80000000U)
936 #define TRGMUX_3_GTM_107_104_LK_SHIFT            (31U)
937 #define TRGMUX_3_GTM_107_104_LK_WIDTH            (1U)
938 #define TRGMUX_3_GTM_107_104_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_107_104_LK_SHIFT)) & TRGMUX_3_GTM_107_104_LK_MASK)
939 /*! @} */
940 
941 /*! @name GTM_111_108 - TRGMUX GTM_111_108 */
942 /*! @{ */
943 
944 #define TRGMUX_3_GTM_111_108_SEL0_MASK           (0x7FU)
945 #define TRGMUX_3_GTM_111_108_SEL0_SHIFT          (0U)
946 #define TRGMUX_3_GTM_111_108_SEL0_WIDTH          (7U)
947 #define TRGMUX_3_GTM_111_108_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_111_108_SEL0_SHIFT)) & TRGMUX_3_GTM_111_108_SEL0_MASK)
948 
949 #define TRGMUX_3_GTM_111_108_SEL1_MASK           (0x7F00U)
950 #define TRGMUX_3_GTM_111_108_SEL1_SHIFT          (8U)
951 #define TRGMUX_3_GTM_111_108_SEL1_WIDTH          (7U)
952 #define TRGMUX_3_GTM_111_108_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_111_108_SEL1_SHIFT)) & TRGMUX_3_GTM_111_108_SEL1_MASK)
953 
954 #define TRGMUX_3_GTM_111_108_SEL2_MASK           (0x7F0000U)
955 #define TRGMUX_3_GTM_111_108_SEL2_SHIFT          (16U)
956 #define TRGMUX_3_GTM_111_108_SEL2_WIDTH          (7U)
957 #define TRGMUX_3_GTM_111_108_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_111_108_SEL2_SHIFT)) & TRGMUX_3_GTM_111_108_SEL2_MASK)
958 
959 #define TRGMUX_3_GTM_111_108_SEL3_MASK           (0x7F000000U)
960 #define TRGMUX_3_GTM_111_108_SEL3_SHIFT          (24U)
961 #define TRGMUX_3_GTM_111_108_SEL3_WIDTH          (7U)
962 #define TRGMUX_3_GTM_111_108_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_111_108_SEL3_SHIFT)) & TRGMUX_3_GTM_111_108_SEL3_MASK)
963 
964 #define TRGMUX_3_GTM_111_108_LK_MASK             (0x80000000U)
965 #define TRGMUX_3_GTM_111_108_LK_SHIFT            (31U)
966 #define TRGMUX_3_GTM_111_108_LK_WIDTH            (1U)
967 #define TRGMUX_3_GTM_111_108_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_111_108_LK_SHIFT)) & TRGMUX_3_GTM_111_108_LK_MASK)
968 /*! @} */
969 
970 /*! @name GTM_115_112 - TRGMUX GTM_115_112 */
971 /*! @{ */
972 
973 #define TRGMUX_3_GTM_115_112_SEL0_MASK           (0x7FU)
974 #define TRGMUX_3_GTM_115_112_SEL0_SHIFT          (0U)
975 #define TRGMUX_3_GTM_115_112_SEL0_WIDTH          (7U)
976 #define TRGMUX_3_GTM_115_112_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_115_112_SEL0_SHIFT)) & TRGMUX_3_GTM_115_112_SEL0_MASK)
977 
978 #define TRGMUX_3_GTM_115_112_SEL1_MASK           (0x7F00U)
979 #define TRGMUX_3_GTM_115_112_SEL1_SHIFT          (8U)
980 #define TRGMUX_3_GTM_115_112_SEL1_WIDTH          (7U)
981 #define TRGMUX_3_GTM_115_112_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_115_112_SEL1_SHIFT)) & TRGMUX_3_GTM_115_112_SEL1_MASK)
982 
983 #define TRGMUX_3_GTM_115_112_SEL2_MASK           (0x7F0000U)
984 #define TRGMUX_3_GTM_115_112_SEL2_SHIFT          (16U)
985 #define TRGMUX_3_GTM_115_112_SEL2_WIDTH          (7U)
986 #define TRGMUX_3_GTM_115_112_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_115_112_SEL2_SHIFT)) & TRGMUX_3_GTM_115_112_SEL2_MASK)
987 
988 #define TRGMUX_3_GTM_115_112_SEL3_MASK           (0x7F000000U)
989 #define TRGMUX_3_GTM_115_112_SEL3_SHIFT          (24U)
990 #define TRGMUX_3_GTM_115_112_SEL3_WIDTH          (7U)
991 #define TRGMUX_3_GTM_115_112_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_115_112_SEL3_SHIFT)) & TRGMUX_3_GTM_115_112_SEL3_MASK)
992 
993 #define TRGMUX_3_GTM_115_112_LK_MASK             (0x80000000U)
994 #define TRGMUX_3_GTM_115_112_LK_SHIFT            (31U)
995 #define TRGMUX_3_GTM_115_112_LK_WIDTH            (1U)
996 #define TRGMUX_3_GTM_115_112_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_115_112_LK_SHIFT)) & TRGMUX_3_GTM_115_112_LK_MASK)
997 /*! @} */
998 
999 /*! @name GTM_119_116 - TRGMUX GTM_119_116 */
1000 /*! @{ */
1001 
1002 #define TRGMUX_3_GTM_119_116_SEL0_MASK           (0x7FU)
1003 #define TRGMUX_3_GTM_119_116_SEL0_SHIFT          (0U)
1004 #define TRGMUX_3_GTM_119_116_SEL0_WIDTH          (7U)
1005 #define TRGMUX_3_GTM_119_116_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_119_116_SEL0_SHIFT)) & TRGMUX_3_GTM_119_116_SEL0_MASK)
1006 
1007 #define TRGMUX_3_GTM_119_116_SEL1_MASK           (0x7F00U)
1008 #define TRGMUX_3_GTM_119_116_SEL1_SHIFT          (8U)
1009 #define TRGMUX_3_GTM_119_116_SEL1_WIDTH          (7U)
1010 #define TRGMUX_3_GTM_119_116_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_119_116_SEL1_SHIFT)) & TRGMUX_3_GTM_119_116_SEL1_MASK)
1011 
1012 #define TRGMUX_3_GTM_119_116_SEL2_MASK           (0x7F0000U)
1013 #define TRGMUX_3_GTM_119_116_SEL2_SHIFT          (16U)
1014 #define TRGMUX_3_GTM_119_116_SEL2_WIDTH          (7U)
1015 #define TRGMUX_3_GTM_119_116_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_119_116_SEL2_SHIFT)) & TRGMUX_3_GTM_119_116_SEL2_MASK)
1016 
1017 #define TRGMUX_3_GTM_119_116_SEL3_MASK           (0x7F000000U)
1018 #define TRGMUX_3_GTM_119_116_SEL3_SHIFT          (24U)
1019 #define TRGMUX_3_GTM_119_116_SEL3_WIDTH          (7U)
1020 #define TRGMUX_3_GTM_119_116_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_119_116_SEL3_SHIFT)) & TRGMUX_3_GTM_119_116_SEL3_MASK)
1021 
1022 #define TRGMUX_3_GTM_119_116_LK_MASK             (0x80000000U)
1023 #define TRGMUX_3_GTM_119_116_LK_SHIFT            (31U)
1024 #define TRGMUX_3_GTM_119_116_LK_WIDTH            (1U)
1025 #define TRGMUX_3_GTM_119_116_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_119_116_LK_SHIFT)) & TRGMUX_3_GTM_119_116_LK_MASK)
1026 /*! @} */
1027 
1028 /*! @name GTM_123_120 - TRGMUX GTM_123_120 */
1029 /*! @{ */
1030 
1031 #define TRGMUX_3_GTM_123_120_SEL0_MASK           (0x7FU)
1032 #define TRGMUX_3_GTM_123_120_SEL0_SHIFT          (0U)
1033 #define TRGMUX_3_GTM_123_120_SEL0_WIDTH          (7U)
1034 #define TRGMUX_3_GTM_123_120_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_123_120_SEL0_SHIFT)) & TRGMUX_3_GTM_123_120_SEL0_MASK)
1035 
1036 #define TRGMUX_3_GTM_123_120_SEL1_MASK           (0x7F00U)
1037 #define TRGMUX_3_GTM_123_120_SEL1_SHIFT          (8U)
1038 #define TRGMUX_3_GTM_123_120_SEL1_WIDTH          (7U)
1039 #define TRGMUX_3_GTM_123_120_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_123_120_SEL1_SHIFT)) & TRGMUX_3_GTM_123_120_SEL1_MASK)
1040 
1041 #define TRGMUX_3_GTM_123_120_SEL2_MASK           (0x7F0000U)
1042 #define TRGMUX_3_GTM_123_120_SEL2_SHIFT          (16U)
1043 #define TRGMUX_3_GTM_123_120_SEL2_WIDTH          (7U)
1044 #define TRGMUX_3_GTM_123_120_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_123_120_SEL2_SHIFT)) & TRGMUX_3_GTM_123_120_SEL2_MASK)
1045 
1046 #define TRGMUX_3_GTM_123_120_SEL3_MASK           (0x7F000000U)
1047 #define TRGMUX_3_GTM_123_120_SEL3_SHIFT          (24U)
1048 #define TRGMUX_3_GTM_123_120_SEL3_WIDTH          (7U)
1049 #define TRGMUX_3_GTM_123_120_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_123_120_SEL3_SHIFT)) & TRGMUX_3_GTM_123_120_SEL3_MASK)
1050 
1051 #define TRGMUX_3_GTM_123_120_LK_MASK             (0x80000000U)
1052 #define TRGMUX_3_GTM_123_120_LK_SHIFT            (31U)
1053 #define TRGMUX_3_GTM_123_120_LK_WIDTH            (1U)
1054 #define TRGMUX_3_GTM_123_120_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_123_120_LK_SHIFT)) & TRGMUX_3_GTM_123_120_LK_MASK)
1055 /*! @} */
1056 
1057 /*! @name GTM_127_124 - TRGMUX GTM_127_124 */
1058 /*! @{ */
1059 
1060 #define TRGMUX_3_GTM_127_124_SEL0_MASK           (0x7FU)
1061 #define TRGMUX_3_GTM_127_124_SEL0_SHIFT          (0U)
1062 #define TRGMUX_3_GTM_127_124_SEL0_WIDTH          (7U)
1063 #define TRGMUX_3_GTM_127_124_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_127_124_SEL0_SHIFT)) & TRGMUX_3_GTM_127_124_SEL0_MASK)
1064 
1065 #define TRGMUX_3_GTM_127_124_SEL1_MASK           (0x7F00U)
1066 #define TRGMUX_3_GTM_127_124_SEL1_SHIFT          (8U)
1067 #define TRGMUX_3_GTM_127_124_SEL1_WIDTH          (7U)
1068 #define TRGMUX_3_GTM_127_124_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_127_124_SEL1_SHIFT)) & TRGMUX_3_GTM_127_124_SEL1_MASK)
1069 
1070 #define TRGMUX_3_GTM_127_124_SEL2_MASK           (0x7F0000U)
1071 #define TRGMUX_3_GTM_127_124_SEL2_SHIFT          (16U)
1072 #define TRGMUX_3_GTM_127_124_SEL2_WIDTH          (7U)
1073 #define TRGMUX_3_GTM_127_124_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_127_124_SEL2_SHIFT)) & TRGMUX_3_GTM_127_124_SEL2_MASK)
1074 
1075 #define TRGMUX_3_GTM_127_124_SEL3_MASK           (0x7F000000U)
1076 #define TRGMUX_3_GTM_127_124_SEL3_SHIFT          (24U)
1077 #define TRGMUX_3_GTM_127_124_SEL3_WIDTH          (7U)
1078 #define TRGMUX_3_GTM_127_124_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_127_124_SEL3_SHIFT)) & TRGMUX_3_GTM_127_124_SEL3_MASK)
1079 
1080 #define TRGMUX_3_GTM_127_124_LK_MASK             (0x80000000U)
1081 #define TRGMUX_3_GTM_127_124_LK_SHIFT            (31U)
1082 #define TRGMUX_3_GTM_127_124_LK_WIDTH            (1U)
1083 #define TRGMUX_3_GTM_127_124_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_127_124_LK_SHIFT)) & TRGMUX_3_GTM_127_124_LK_MASK)
1084 /*! @} */
1085 
1086 /*! @name GTM_131_128 - TRGMUX GTM_131_128 */
1087 /*! @{ */
1088 
1089 #define TRGMUX_3_GTM_131_128_SEL0_MASK           (0x7FU)
1090 #define TRGMUX_3_GTM_131_128_SEL0_SHIFT          (0U)
1091 #define TRGMUX_3_GTM_131_128_SEL0_WIDTH          (7U)
1092 #define TRGMUX_3_GTM_131_128_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_131_128_SEL0_SHIFT)) & TRGMUX_3_GTM_131_128_SEL0_MASK)
1093 
1094 #define TRGMUX_3_GTM_131_128_SEL1_MASK           (0x7F00U)
1095 #define TRGMUX_3_GTM_131_128_SEL1_SHIFT          (8U)
1096 #define TRGMUX_3_GTM_131_128_SEL1_WIDTH          (7U)
1097 #define TRGMUX_3_GTM_131_128_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_131_128_SEL1_SHIFT)) & TRGMUX_3_GTM_131_128_SEL1_MASK)
1098 
1099 #define TRGMUX_3_GTM_131_128_SEL2_MASK           (0x7F0000U)
1100 #define TRGMUX_3_GTM_131_128_SEL2_SHIFT          (16U)
1101 #define TRGMUX_3_GTM_131_128_SEL2_WIDTH          (7U)
1102 #define TRGMUX_3_GTM_131_128_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_131_128_SEL2_SHIFT)) & TRGMUX_3_GTM_131_128_SEL2_MASK)
1103 
1104 #define TRGMUX_3_GTM_131_128_SEL3_MASK           (0x7F000000U)
1105 #define TRGMUX_3_GTM_131_128_SEL3_SHIFT          (24U)
1106 #define TRGMUX_3_GTM_131_128_SEL3_WIDTH          (7U)
1107 #define TRGMUX_3_GTM_131_128_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_131_128_SEL3_SHIFT)) & TRGMUX_3_GTM_131_128_SEL3_MASK)
1108 
1109 #define TRGMUX_3_GTM_131_128_LK_MASK             (0x80000000U)
1110 #define TRGMUX_3_GTM_131_128_LK_SHIFT            (31U)
1111 #define TRGMUX_3_GTM_131_128_LK_WIDTH            (1U)
1112 #define TRGMUX_3_GTM_131_128_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_131_128_LK_SHIFT)) & TRGMUX_3_GTM_131_128_LK_MASK)
1113 /*! @} */
1114 
1115 /*! @name GTM_135_132 - TRGMUX GTM_135_132 */
1116 /*! @{ */
1117 
1118 #define TRGMUX_3_GTM_135_132_SEL0_MASK           (0x7FU)
1119 #define TRGMUX_3_GTM_135_132_SEL0_SHIFT          (0U)
1120 #define TRGMUX_3_GTM_135_132_SEL0_WIDTH          (7U)
1121 #define TRGMUX_3_GTM_135_132_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_135_132_SEL0_SHIFT)) & TRGMUX_3_GTM_135_132_SEL0_MASK)
1122 
1123 #define TRGMUX_3_GTM_135_132_SEL1_MASK           (0x7F00U)
1124 #define TRGMUX_3_GTM_135_132_SEL1_SHIFT          (8U)
1125 #define TRGMUX_3_GTM_135_132_SEL1_WIDTH          (7U)
1126 #define TRGMUX_3_GTM_135_132_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_135_132_SEL1_SHIFT)) & TRGMUX_3_GTM_135_132_SEL1_MASK)
1127 
1128 #define TRGMUX_3_GTM_135_132_SEL2_MASK           (0x7F0000U)
1129 #define TRGMUX_3_GTM_135_132_SEL2_SHIFT          (16U)
1130 #define TRGMUX_3_GTM_135_132_SEL2_WIDTH          (7U)
1131 #define TRGMUX_3_GTM_135_132_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_135_132_SEL2_SHIFT)) & TRGMUX_3_GTM_135_132_SEL2_MASK)
1132 
1133 #define TRGMUX_3_GTM_135_132_SEL3_MASK           (0x7F000000U)
1134 #define TRGMUX_3_GTM_135_132_SEL3_SHIFT          (24U)
1135 #define TRGMUX_3_GTM_135_132_SEL3_WIDTH          (7U)
1136 #define TRGMUX_3_GTM_135_132_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_135_132_SEL3_SHIFT)) & TRGMUX_3_GTM_135_132_SEL3_MASK)
1137 
1138 #define TRGMUX_3_GTM_135_132_LK_MASK             (0x80000000U)
1139 #define TRGMUX_3_GTM_135_132_LK_SHIFT            (31U)
1140 #define TRGMUX_3_GTM_135_132_LK_WIDTH            (1U)
1141 #define TRGMUX_3_GTM_135_132_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_135_132_LK_SHIFT)) & TRGMUX_3_GTM_135_132_LK_MASK)
1142 /*! @} */
1143 
1144 /*! @name GTM_139_136 - TRGMUX GTM_139_136 */
1145 /*! @{ */
1146 
1147 #define TRGMUX_3_GTM_139_136_SEL0_MASK           (0x7FU)
1148 #define TRGMUX_3_GTM_139_136_SEL0_SHIFT          (0U)
1149 #define TRGMUX_3_GTM_139_136_SEL0_WIDTH          (7U)
1150 #define TRGMUX_3_GTM_139_136_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_139_136_SEL0_SHIFT)) & TRGMUX_3_GTM_139_136_SEL0_MASK)
1151 
1152 #define TRGMUX_3_GTM_139_136_SEL1_MASK           (0x7F00U)
1153 #define TRGMUX_3_GTM_139_136_SEL1_SHIFT          (8U)
1154 #define TRGMUX_3_GTM_139_136_SEL1_WIDTH          (7U)
1155 #define TRGMUX_3_GTM_139_136_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_139_136_SEL1_SHIFT)) & TRGMUX_3_GTM_139_136_SEL1_MASK)
1156 
1157 #define TRGMUX_3_GTM_139_136_SEL2_MASK           (0x7F0000U)
1158 #define TRGMUX_3_GTM_139_136_SEL2_SHIFT          (16U)
1159 #define TRGMUX_3_GTM_139_136_SEL2_WIDTH          (7U)
1160 #define TRGMUX_3_GTM_139_136_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_139_136_SEL2_SHIFT)) & TRGMUX_3_GTM_139_136_SEL2_MASK)
1161 
1162 #define TRGMUX_3_GTM_139_136_SEL3_MASK           (0x7F000000U)
1163 #define TRGMUX_3_GTM_139_136_SEL3_SHIFT          (24U)
1164 #define TRGMUX_3_GTM_139_136_SEL3_WIDTH          (7U)
1165 #define TRGMUX_3_GTM_139_136_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_139_136_SEL3_SHIFT)) & TRGMUX_3_GTM_139_136_SEL3_MASK)
1166 
1167 #define TRGMUX_3_GTM_139_136_LK_MASK             (0x80000000U)
1168 #define TRGMUX_3_GTM_139_136_LK_SHIFT            (31U)
1169 #define TRGMUX_3_GTM_139_136_LK_WIDTH            (1U)
1170 #define TRGMUX_3_GTM_139_136_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_139_136_LK_SHIFT)) & TRGMUX_3_GTM_139_136_LK_MASK)
1171 /*! @} */
1172 
1173 /*! @name GTM_143_140 - TRGMUX GTM_143_140 */
1174 /*! @{ */
1175 
1176 #define TRGMUX_3_GTM_143_140_SEL0_MASK           (0x7FU)
1177 #define TRGMUX_3_GTM_143_140_SEL0_SHIFT          (0U)
1178 #define TRGMUX_3_GTM_143_140_SEL0_WIDTH          (7U)
1179 #define TRGMUX_3_GTM_143_140_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_143_140_SEL0_SHIFT)) & TRGMUX_3_GTM_143_140_SEL0_MASK)
1180 
1181 #define TRGMUX_3_GTM_143_140_SEL1_MASK           (0x7F00U)
1182 #define TRGMUX_3_GTM_143_140_SEL1_SHIFT          (8U)
1183 #define TRGMUX_3_GTM_143_140_SEL1_WIDTH          (7U)
1184 #define TRGMUX_3_GTM_143_140_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_143_140_SEL1_SHIFT)) & TRGMUX_3_GTM_143_140_SEL1_MASK)
1185 
1186 #define TRGMUX_3_GTM_143_140_SEL2_MASK           (0x7F0000U)
1187 #define TRGMUX_3_GTM_143_140_SEL2_SHIFT          (16U)
1188 #define TRGMUX_3_GTM_143_140_SEL2_WIDTH          (7U)
1189 #define TRGMUX_3_GTM_143_140_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_143_140_SEL2_SHIFT)) & TRGMUX_3_GTM_143_140_SEL2_MASK)
1190 
1191 #define TRGMUX_3_GTM_143_140_SEL3_MASK           (0x7F000000U)
1192 #define TRGMUX_3_GTM_143_140_SEL3_SHIFT          (24U)
1193 #define TRGMUX_3_GTM_143_140_SEL3_WIDTH          (7U)
1194 #define TRGMUX_3_GTM_143_140_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_143_140_SEL3_SHIFT)) & TRGMUX_3_GTM_143_140_SEL3_MASK)
1195 
1196 #define TRGMUX_3_GTM_143_140_LK_MASK             (0x80000000U)
1197 #define TRGMUX_3_GTM_143_140_LK_SHIFT            (31U)
1198 #define TRGMUX_3_GTM_143_140_LK_WIDTH            (1U)
1199 #define TRGMUX_3_GTM_143_140_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_143_140_LK_SHIFT)) & TRGMUX_3_GTM_143_140_LK_MASK)
1200 /*! @} */
1201 
1202 /*! @name GTM_147_144 - TRGMUX GTM_147_144 */
1203 /*! @{ */
1204 
1205 #define TRGMUX_3_GTM_147_144_SEL0_MASK           (0x7FU)
1206 #define TRGMUX_3_GTM_147_144_SEL0_SHIFT          (0U)
1207 #define TRGMUX_3_GTM_147_144_SEL0_WIDTH          (7U)
1208 #define TRGMUX_3_GTM_147_144_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_147_144_SEL0_SHIFT)) & TRGMUX_3_GTM_147_144_SEL0_MASK)
1209 
1210 #define TRGMUX_3_GTM_147_144_SEL1_MASK           (0x7F00U)
1211 #define TRGMUX_3_GTM_147_144_SEL1_SHIFT          (8U)
1212 #define TRGMUX_3_GTM_147_144_SEL1_WIDTH          (7U)
1213 #define TRGMUX_3_GTM_147_144_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_147_144_SEL1_SHIFT)) & TRGMUX_3_GTM_147_144_SEL1_MASK)
1214 
1215 #define TRGMUX_3_GTM_147_144_SEL2_MASK           (0x7F0000U)
1216 #define TRGMUX_3_GTM_147_144_SEL2_SHIFT          (16U)
1217 #define TRGMUX_3_GTM_147_144_SEL2_WIDTH          (7U)
1218 #define TRGMUX_3_GTM_147_144_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_147_144_SEL2_SHIFT)) & TRGMUX_3_GTM_147_144_SEL2_MASK)
1219 
1220 #define TRGMUX_3_GTM_147_144_SEL3_MASK           (0x7F000000U)
1221 #define TRGMUX_3_GTM_147_144_SEL3_SHIFT          (24U)
1222 #define TRGMUX_3_GTM_147_144_SEL3_WIDTH          (7U)
1223 #define TRGMUX_3_GTM_147_144_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_147_144_SEL3_SHIFT)) & TRGMUX_3_GTM_147_144_SEL3_MASK)
1224 
1225 #define TRGMUX_3_GTM_147_144_LK_MASK             (0x80000000U)
1226 #define TRGMUX_3_GTM_147_144_LK_SHIFT            (31U)
1227 #define TRGMUX_3_GTM_147_144_LK_WIDTH            (1U)
1228 #define TRGMUX_3_GTM_147_144_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_147_144_LK_SHIFT)) & TRGMUX_3_GTM_147_144_LK_MASK)
1229 /*! @} */
1230 
1231 /*! @name GTM_151_148 - TRGMUX GTM_151_148 */
1232 /*! @{ */
1233 
1234 #define TRGMUX_3_GTM_151_148_SEL0_MASK           (0x7FU)
1235 #define TRGMUX_3_GTM_151_148_SEL0_SHIFT          (0U)
1236 #define TRGMUX_3_GTM_151_148_SEL0_WIDTH          (7U)
1237 #define TRGMUX_3_GTM_151_148_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_151_148_SEL0_SHIFT)) & TRGMUX_3_GTM_151_148_SEL0_MASK)
1238 
1239 #define TRGMUX_3_GTM_151_148_SEL1_MASK           (0x7F00U)
1240 #define TRGMUX_3_GTM_151_148_SEL1_SHIFT          (8U)
1241 #define TRGMUX_3_GTM_151_148_SEL1_WIDTH          (7U)
1242 #define TRGMUX_3_GTM_151_148_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_151_148_SEL1_SHIFT)) & TRGMUX_3_GTM_151_148_SEL1_MASK)
1243 
1244 #define TRGMUX_3_GTM_151_148_SEL2_MASK           (0x7F0000U)
1245 #define TRGMUX_3_GTM_151_148_SEL2_SHIFT          (16U)
1246 #define TRGMUX_3_GTM_151_148_SEL2_WIDTH          (7U)
1247 #define TRGMUX_3_GTM_151_148_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_151_148_SEL2_SHIFT)) & TRGMUX_3_GTM_151_148_SEL2_MASK)
1248 
1249 #define TRGMUX_3_GTM_151_148_SEL3_MASK           (0x7F000000U)
1250 #define TRGMUX_3_GTM_151_148_SEL3_SHIFT          (24U)
1251 #define TRGMUX_3_GTM_151_148_SEL3_WIDTH          (7U)
1252 #define TRGMUX_3_GTM_151_148_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_151_148_SEL3_SHIFT)) & TRGMUX_3_GTM_151_148_SEL3_MASK)
1253 
1254 #define TRGMUX_3_GTM_151_148_LK_MASK             (0x80000000U)
1255 #define TRGMUX_3_GTM_151_148_LK_SHIFT            (31U)
1256 #define TRGMUX_3_GTM_151_148_LK_WIDTH            (1U)
1257 #define TRGMUX_3_GTM_151_148_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_151_148_LK_SHIFT)) & TRGMUX_3_GTM_151_148_LK_MASK)
1258 /*! @} */
1259 
1260 /*! @name GTM_155_152 - TRGMUX GTM_155_152 */
1261 /*! @{ */
1262 
1263 #define TRGMUX_3_GTM_155_152_SEL0_MASK           (0x7FU)
1264 #define TRGMUX_3_GTM_155_152_SEL0_SHIFT          (0U)
1265 #define TRGMUX_3_GTM_155_152_SEL0_WIDTH          (7U)
1266 #define TRGMUX_3_GTM_155_152_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_155_152_SEL0_SHIFT)) & TRGMUX_3_GTM_155_152_SEL0_MASK)
1267 
1268 #define TRGMUX_3_GTM_155_152_SEL1_MASK           (0x7F00U)
1269 #define TRGMUX_3_GTM_155_152_SEL1_SHIFT          (8U)
1270 #define TRGMUX_3_GTM_155_152_SEL1_WIDTH          (7U)
1271 #define TRGMUX_3_GTM_155_152_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_155_152_SEL1_SHIFT)) & TRGMUX_3_GTM_155_152_SEL1_MASK)
1272 
1273 #define TRGMUX_3_GTM_155_152_SEL2_MASK           (0x7F0000U)
1274 #define TRGMUX_3_GTM_155_152_SEL2_SHIFT          (16U)
1275 #define TRGMUX_3_GTM_155_152_SEL2_WIDTH          (7U)
1276 #define TRGMUX_3_GTM_155_152_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_155_152_SEL2_SHIFT)) & TRGMUX_3_GTM_155_152_SEL2_MASK)
1277 
1278 #define TRGMUX_3_GTM_155_152_SEL3_MASK           (0x7F000000U)
1279 #define TRGMUX_3_GTM_155_152_SEL3_SHIFT          (24U)
1280 #define TRGMUX_3_GTM_155_152_SEL3_WIDTH          (7U)
1281 #define TRGMUX_3_GTM_155_152_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_155_152_SEL3_SHIFT)) & TRGMUX_3_GTM_155_152_SEL3_MASK)
1282 
1283 #define TRGMUX_3_GTM_155_152_LK_MASK             (0x80000000U)
1284 #define TRGMUX_3_GTM_155_152_LK_SHIFT            (31U)
1285 #define TRGMUX_3_GTM_155_152_LK_WIDTH            (1U)
1286 #define TRGMUX_3_GTM_155_152_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_155_152_LK_SHIFT)) & TRGMUX_3_GTM_155_152_LK_MASK)
1287 /*! @} */
1288 
1289 /*! @name GTM_159_156 - TRGMUX GTM_159_156 */
1290 /*! @{ */
1291 
1292 #define TRGMUX_3_GTM_159_156_SEL0_MASK           (0x7FU)
1293 #define TRGMUX_3_GTM_159_156_SEL0_SHIFT          (0U)
1294 #define TRGMUX_3_GTM_159_156_SEL0_WIDTH          (7U)
1295 #define TRGMUX_3_GTM_159_156_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_159_156_SEL0_SHIFT)) & TRGMUX_3_GTM_159_156_SEL0_MASK)
1296 
1297 #define TRGMUX_3_GTM_159_156_SEL1_MASK           (0x7F00U)
1298 #define TRGMUX_3_GTM_159_156_SEL1_SHIFT          (8U)
1299 #define TRGMUX_3_GTM_159_156_SEL1_WIDTH          (7U)
1300 #define TRGMUX_3_GTM_159_156_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_159_156_SEL1_SHIFT)) & TRGMUX_3_GTM_159_156_SEL1_MASK)
1301 
1302 #define TRGMUX_3_GTM_159_156_SEL2_MASK           (0x7F0000U)
1303 #define TRGMUX_3_GTM_159_156_SEL2_SHIFT          (16U)
1304 #define TRGMUX_3_GTM_159_156_SEL2_WIDTH          (7U)
1305 #define TRGMUX_3_GTM_159_156_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_159_156_SEL2_SHIFT)) & TRGMUX_3_GTM_159_156_SEL2_MASK)
1306 
1307 #define TRGMUX_3_GTM_159_156_SEL3_MASK           (0x7F000000U)
1308 #define TRGMUX_3_GTM_159_156_SEL3_SHIFT          (24U)
1309 #define TRGMUX_3_GTM_159_156_SEL3_WIDTH          (7U)
1310 #define TRGMUX_3_GTM_159_156_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_159_156_SEL3_SHIFT)) & TRGMUX_3_GTM_159_156_SEL3_MASK)
1311 
1312 #define TRGMUX_3_GTM_159_156_LK_MASK             (0x80000000U)
1313 #define TRGMUX_3_GTM_159_156_LK_SHIFT            (31U)
1314 #define TRGMUX_3_GTM_159_156_LK_WIDTH            (1U)
1315 #define TRGMUX_3_GTM_159_156_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_159_156_LK_SHIFT)) & TRGMUX_3_GTM_159_156_LK_MASK)
1316 /*! @} */
1317 
1318 /*! @name GTM_163_160 - TRGMUX GTM_163_160 */
1319 /*! @{ */
1320 
1321 #define TRGMUX_3_GTM_163_160_SEL0_MASK           (0x7FU)
1322 #define TRGMUX_3_GTM_163_160_SEL0_SHIFT          (0U)
1323 #define TRGMUX_3_GTM_163_160_SEL0_WIDTH          (7U)
1324 #define TRGMUX_3_GTM_163_160_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_163_160_SEL0_SHIFT)) & TRGMUX_3_GTM_163_160_SEL0_MASK)
1325 
1326 #define TRGMUX_3_GTM_163_160_SEL1_MASK           (0x7F00U)
1327 #define TRGMUX_3_GTM_163_160_SEL1_SHIFT          (8U)
1328 #define TRGMUX_3_GTM_163_160_SEL1_WIDTH          (7U)
1329 #define TRGMUX_3_GTM_163_160_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_163_160_SEL1_SHIFT)) & TRGMUX_3_GTM_163_160_SEL1_MASK)
1330 
1331 #define TRGMUX_3_GTM_163_160_SEL2_MASK           (0x7F0000U)
1332 #define TRGMUX_3_GTM_163_160_SEL2_SHIFT          (16U)
1333 #define TRGMUX_3_GTM_163_160_SEL2_WIDTH          (7U)
1334 #define TRGMUX_3_GTM_163_160_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_163_160_SEL2_SHIFT)) & TRGMUX_3_GTM_163_160_SEL2_MASK)
1335 
1336 #define TRGMUX_3_GTM_163_160_SEL3_MASK           (0x7F000000U)
1337 #define TRGMUX_3_GTM_163_160_SEL3_SHIFT          (24U)
1338 #define TRGMUX_3_GTM_163_160_SEL3_WIDTH          (7U)
1339 #define TRGMUX_3_GTM_163_160_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_163_160_SEL3_SHIFT)) & TRGMUX_3_GTM_163_160_SEL3_MASK)
1340 
1341 #define TRGMUX_3_GTM_163_160_LK_MASK             (0x80000000U)
1342 #define TRGMUX_3_GTM_163_160_LK_SHIFT            (31U)
1343 #define TRGMUX_3_GTM_163_160_LK_WIDTH            (1U)
1344 #define TRGMUX_3_GTM_163_160_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_163_160_LK_SHIFT)) & TRGMUX_3_GTM_163_160_LK_MASK)
1345 /*! @} */
1346 
1347 /*! @name GTM_167_164 - TRGMUX GTM_167_164 */
1348 /*! @{ */
1349 
1350 #define TRGMUX_3_GTM_167_164_SEL0_MASK           (0x7FU)
1351 #define TRGMUX_3_GTM_167_164_SEL0_SHIFT          (0U)
1352 #define TRGMUX_3_GTM_167_164_SEL0_WIDTH          (7U)
1353 #define TRGMUX_3_GTM_167_164_SEL0(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_167_164_SEL0_SHIFT)) & TRGMUX_3_GTM_167_164_SEL0_MASK)
1354 
1355 #define TRGMUX_3_GTM_167_164_SEL1_MASK           (0x7F00U)
1356 #define TRGMUX_3_GTM_167_164_SEL1_SHIFT          (8U)
1357 #define TRGMUX_3_GTM_167_164_SEL1_WIDTH          (7U)
1358 #define TRGMUX_3_GTM_167_164_SEL1(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_167_164_SEL1_SHIFT)) & TRGMUX_3_GTM_167_164_SEL1_MASK)
1359 
1360 #define TRGMUX_3_GTM_167_164_SEL2_MASK           (0x7F0000U)
1361 #define TRGMUX_3_GTM_167_164_SEL2_SHIFT          (16U)
1362 #define TRGMUX_3_GTM_167_164_SEL2_WIDTH          (7U)
1363 #define TRGMUX_3_GTM_167_164_SEL2(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_167_164_SEL2_SHIFT)) & TRGMUX_3_GTM_167_164_SEL2_MASK)
1364 
1365 #define TRGMUX_3_GTM_167_164_SEL3_MASK           (0x7F000000U)
1366 #define TRGMUX_3_GTM_167_164_SEL3_SHIFT          (24U)
1367 #define TRGMUX_3_GTM_167_164_SEL3_WIDTH          (7U)
1368 #define TRGMUX_3_GTM_167_164_SEL3(x)             (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_167_164_SEL3_SHIFT)) & TRGMUX_3_GTM_167_164_SEL3_MASK)
1369 
1370 #define TRGMUX_3_GTM_167_164_LK_MASK             (0x80000000U)
1371 #define TRGMUX_3_GTM_167_164_LK_SHIFT            (31U)
1372 #define TRGMUX_3_GTM_167_164_LK_WIDTH            (1U)
1373 #define TRGMUX_3_GTM_167_164_LK(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_167_164_LK_SHIFT)) & TRGMUX_3_GTM_167_164_LK_MASK)
1374 /*! @} */
1375 
1376 /*! @name GTM_168 - TRGMUX GTM_168 */
1377 /*! @{ */
1378 
1379 #define TRGMUX_3_GTM_168_SEL0_MASK               (0x7FU)
1380 #define TRGMUX_3_GTM_168_SEL0_SHIFT              (0U)
1381 #define TRGMUX_3_GTM_168_SEL0_WIDTH              (7U)
1382 #define TRGMUX_3_GTM_168_SEL0(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_168_SEL0_SHIFT)) & TRGMUX_3_GTM_168_SEL0_MASK)
1383 
1384 #define TRGMUX_3_GTM_168_LK_MASK                 (0x80000000U)
1385 #define TRGMUX_3_GTM_168_LK_SHIFT                (31U)
1386 #define TRGMUX_3_GTM_168_LK_WIDTH                (1U)
1387 #define TRGMUX_3_GTM_168_LK(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_GTM_168_LK_SHIFT)) & TRGMUX_3_GTM_168_LK_MASK)
1388 /*! @} */
1389 
1390 /*! @name MSC_03_00 - TRGMUX MSC_03_00 */
1391 /*! @{ */
1392 
1393 #define TRGMUX_3_MSC_03_00_SEL0_MASK             (0x7FU)
1394 #define TRGMUX_3_MSC_03_00_SEL0_SHIFT            (0U)
1395 #define TRGMUX_3_MSC_03_00_SEL0_WIDTH            (7U)
1396 #define TRGMUX_3_MSC_03_00_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_03_00_SEL0_SHIFT)) & TRGMUX_3_MSC_03_00_SEL0_MASK)
1397 
1398 #define TRGMUX_3_MSC_03_00_SEL1_MASK             (0x7F00U)
1399 #define TRGMUX_3_MSC_03_00_SEL1_SHIFT            (8U)
1400 #define TRGMUX_3_MSC_03_00_SEL1_WIDTH            (7U)
1401 #define TRGMUX_3_MSC_03_00_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_03_00_SEL1_SHIFT)) & TRGMUX_3_MSC_03_00_SEL1_MASK)
1402 
1403 #define TRGMUX_3_MSC_03_00_SEL2_MASK             (0x7F0000U)
1404 #define TRGMUX_3_MSC_03_00_SEL2_SHIFT            (16U)
1405 #define TRGMUX_3_MSC_03_00_SEL2_WIDTH            (7U)
1406 #define TRGMUX_3_MSC_03_00_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_03_00_SEL2_SHIFT)) & TRGMUX_3_MSC_03_00_SEL2_MASK)
1407 
1408 #define TRGMUX_3_MSC_03_00_SEL3_MASK             (0x7F000000U)
1409 #define TRGMUX_3_MSC_03_00_SEL3_SHIFT            (24U)
1410 #define TRGMUX_3_MSC_03_00_SEL3_WIDTH            (7U)
1411 #define TRGMUX_3_MSC_03_00_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_03_00_SEL3_SHIFT)) & TRGMUX_3_MSC_03_00_SEL3_MASK)
1412 
1413 #define TRGMUX_3_MSC_03_00_LK_MASK               (0x80000000U)
1414 #define TRGMUX_3_MSC_03_00_LK_SHIFT              (31U)
1415 #define TRGMUX_3_MSC_03_00_LK_WIDTH              (1U)
1416 #define TRGMUX_3_MSC_03_00_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_03_00_LK_SHIFT)) & TRGMUX_3_MSC_03_00_LK_MASK)
1417 /*! @} */
1418 
1419 /*! @name MSC_07_04 - TRGMUX MSC_07_04 */
1420 /*! @{ */
1421 
1422 #define TRGMUX_3_MSC_07_04_SEL0_MASK             (0x7FU)
1423 #define TRGMUX_3_MSC_07_04_SEL0_SHIFT            (0U)
1424 #define TRGMUX_3_MSC_07_04_SEL0_WIDTH            (7U)
1425 #define TRGMUX_3_MSC_07_04_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_07_04_SEL0_SHIFT)) & TRGMUX_3_MSC_07_04_SEL0_MASK)
1426 
1427 #define TRGMUX_3_MSC_07_04_SEL1_MASK             (0x7F00U)
1428 #define TRGMUX_3_MSC_07_04_SEL1_SHIFT            (8U)
1429 #define TRGMUX_3_MSC_07_04_SEL1_WIDTH            (7U)
1430 #define TRGMUX_3_MSC_07_04_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_07_04_SEL1_SHIFT)) & TRGMUX_3_MSC_07_04_SEL1_MASK)
1431 
1432 #define TRGMUX_3_MSC_07_04_SEL2_MASK             (0x7F0000U)
1433 #define TRGMUX_3_MSC_07_04_SEL2_SHIFT            (16U)
1434 #define TRGMUX_3_MSC_07_04_SEL2_WIDTH            (7U)
1435 #define TRGMUX_3_MSC_07_04_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_07_04_SEL2_SHIFT)) & TRGMUX_3_MSC_07_04_SEL2_MASK)
1436 
1437 #define TRGMUX_3_MSC_07_04_SEL3_MASK             (0x7F000000U)
1438 #define TRGMUX_3_MSC_07_04_SEL3_SHIFT            (24U)
1439 #define TRGMUX_3_MSC_07_04_SEL3_WIDTH            (7U)
1440 #define TRGMUX_3_MSC_07_04_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_07_04_SEL3_SHIFT)) & TRGMUX_3_MSC_07_04_SEL3_MASK)
1441 
1442 #define TRGMUX_3_MSC_07_04_LK_MASK               (0x80000000U)
1443 #define TRGMUX_3_MSC_07_04_LK_SHIFT              (31U)
1444 #define TRGMUX_3_MSC_07_04_LK_WIDTH              (1U)
1445 #define TRGMUX_3_MSC_07_04_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_07_04_LK_SHIFT)) & TRGMUX_3_MSC_07_04_LK_MASK)
1446 /*! @} */
1447 
1448 /*! @name MSC_11_08 - TRGMUX MSC_11_08 */
1449 /*! @{ */
1450 
1451 #define TRGMUX_3_MSC_11_08_SEL0_MASK             (0x7FU)
1452 #define TRGMUX_3_MSC_11_08_SEL0_SHIFT            (0U)
1453 #define TRGMUX_3_MSC_11_08_SEL0_WIDTH            (7U)
1454 #define TRGMUX_3_MSC_11_08_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_11_08_SEL0_SHIFT)) & TRGMUX_3_MSC_11_08_SEL0_MASK)
1455 
1456 #define TRGMUX_3_MSC_11_08_SEL1_MASK             (0x7F00U)
1457 #define TRGMUX_3_MSC_11_08_SEL1_SHIFT            (8U)
1458 #define TRGMUX_3_MSC_11_08_SEL1_WIDTH            (7U)
1459 #define TRGMUX_3_MSC_11_08_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_11_08_SEL1_SHIFT)) & TRGMUX_3_MSC_11_08_SEL1_MASK)
1460 
1461 #define TRGMUX_3_MSC_11_08_SEL2_MASK             (0x7F0000U)
1462 #define TRGMUX_3_MSC_11_08_SEL2_SHIFT            (16U)
1463 #define TRGMUX_3_MSC_11_08_SEL2_WIDTH            (7U)
1464 #define TRGMUX_3_MSC_11_08_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_11_08_SEL2_SHIFT)) & TRGMUX_3_MSC_11_08_SEL2_MASK)
1465 
1466 #define TRGMUX_3_MSC_11_08_SEL3_MASK             (0x7F000000U)
1467 #define TRGMUX_3_MSC_11_08_SEL3_SHIFT            (24U)
1468 #define TRGMUX_3_MSC_11_08_SEL3_WIDTH            (7U)
1469 #define TRGMUX_3_MSC_11_08_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_11_08_SEL3_SHIFT)) & TRGMUX_3_MSC_11_08_SEL3_MASK)
1470 
1471 #define TRGMUX_3_MSC_11_08_LK_MASK               (0x80000000U)
1472 #define TRGMUX_3_MSC_11_08_LK_SHIFT              (31U)
1473 #define TRGMUX_3_MSC_11_08_LK_WIDTH              (1U)
1474 #define TRGMUX_3_MSC_11_08_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_11_08_LK_SHIFT)) & TRGMUX_3_MSC_11_08_LK_MASK)
1475 /*! @} */
1476 
1477 /*! @name MSC_15_12 - TRGMUX MSC_15_12 */
1478 /*! @{ */
1479 
1480 #define TRGMUX_3_MSC_15_12_SEL0_MASK             (0x7FU)
1481 #define TRGMUX_3_MSC_15_12_SEL0_SHIFT            (0U)
1482 #define TRGMUX_3_MSC_15_12_SEL0_WIDTH            (7U)
1483 #define TRGMUX_3_MSC_15_12_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_15_12_SEL0_SHIFT)) & TRGMUX_3_MSC_15_12_SEL0_MASK)
1484 
1485 #define TRGMUX_3_MSC_15_12_SEL1_MASK             (0x7F00U)
1486 #define TRGMUX_3_MSC_15_12_SEL1_SHIFT            (8U)
1487 #define TRGMUX_3_MSC_15_12_SEL1_WIDTH            (7U)
1488 #define TRGMUX_3_MSC_15_12_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_15_12_SEL1_SHIFT)) & TRGMUX_3_MSC_15_12_SEL1_MASK)
1489 
1490 #define TRGMUX_3_MSC_15_12_SEL2_MASK             (0x7F0000U)
1491 #define TRGMUX_3_MSC_15_12_SEL2_SHIFT            (16U)
1492 #define TRGMUX_3_MSC_15_12_SEL2_WIDTH            (7U)
1493 #define TRGMUX_3_MSC_15_12_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_15_12_SEL2_SHIFT)) & TRGMUX_3_MSC_15_12_SEL2_MASK)
1494 
1495 #define TRGMUX_3_MSC_15_12_SEL3_MASK             (0x7F000000U)
1496 #define TRGMUX_3_MSC_15_12_SEL3_SHIFT            (24U)
1497 #define TRGMUX_3_MSC_15_12_SEL3_WIDTH            (7U)
1498 #define TRGMUX_3_MSC_15_12_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_15_12_SEL3_SHIFT)) & TRGMUX_3_MSC_15_12_SEL3_MASK)
1499 
1500 #define TRGMUX_3_MSC_15_12_LK_MASK               (0x80000000U)
1501 #define TRGMUX_3_MSC_15_12_LK_SHIFT              (31U)
1502 #define TRGMUX_3_MSC_15_12_LK_WIDTH              (1U)
1503 #define TRGMUX_3_MSC_15_12_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_15_12_LK_SHIFT)) & TRGMUX_3_MSC_15_12_LK_MASK)
1504 /*! @} */
1505 
1506 /*! @name MSC_19_16 - TRGMUX MSC_19_16 */
1507 /*! @{ */
1508 
1509 #define TRGMUX_3_MSC_19_16_SEL0_MASK             (0x7FU)
1510 #define TRGMUX_3_MSC_19_16_SEL0_SHIFT            (0U)
1511 #define TRGMUX_3_MSC_19_16_SEL0_WIDTH            (7U)
1512 #define TRGMUX_3_MSC_19_16_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_19_16_SEL0_SHIFT)) & TRGMUX_3_MSC_19_16_SEL0_MASK)
1513 
1514 #define TRGMUX_3_MSC_19_16_SEL1_MASK             (0x7F00U)
1515 #define TRGMUX_3_MSC_19_16_SEL1_SHIFT            (8U)
1516 #define TRGMUX_3_MSC_19_16_SEL1_WIDTH            (7U)
1517 #define TRGMUX_3_MSC_19_16_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_19_16_SEL1_SHIFT)) & TRGMUX_3_MSC_19_16_SEL1_MASK)
1518 
1519 #define TRGMUX_3_MSC_19_16_SEL2_MASK             (0x7F0000U)
1520 #define TRGMUX_3_MSC_19_16_SEL2_SHIFT            (16U)
1521 #define TRGMUX_3_MSC_19_16_SEL2_WIDTH            (7U)
1522 #define TRGMUX_3_MSC_19_16_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_19_16_SEL2_SHIFT)) & TRGMUX_3_MSC_19_16_SEL2_MASK)
1523 
1524 #define TRGMUX_3_MSC_19_16_SEL3_MASK             (0x7F000000U)
1525 #define TRGMUX_3_MSC_19_16_SEL3_SHIFT            (24U)
1526 #define TRGMUX_3_MSC_19_16_SEL3_WIDTH            (7U)
1527 #define TRGMUX_3_MSC_19_16_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_19_16_SEL3_SHIFT)) & TRGMUX_3_MSC_19_16_SEL3_MASK)
1528 
1529 #define TRGMUX_3_MSC_19_16_LK_MASK               (0x80000000U)
1530 #define TRGMUX_3_MSC_19_16_LK_SHIFT              (31U)
1531 #define TRGMUX_3_MSC_19_16_LK_WIDTH              (1U)
1532 #define TRGMUX_3_MSC_19_16_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_19_16_LK_SHIFT)) & TRGMUX_3_MSC_19_16_LK_MASK)
1533 /*! @} */
1534 
1535 /*! @name MSC_23_20 - TRGMUX MSC_23_20 */
1536 /*! @{ */
1537 
1538 #define TRGMUX_3_MSC_23_20_SEL0_MASK             (0x7FU)
1539 #define TRGMUX_3_MSC_23_20_SEL0_SHIFT            (0U)
1540 #define TRGMUX_3_MSC_23_20_SEL0_WIDTH            (7U)
1541 #define TRGMUX_3_MSC_23_20_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_23_20_SEL0_SHIFT)) & TRGMUX_3_MSC_23_20_SEL0_MASK)
1542 
1543 #define TRGMUX_3_MSC_23_20_SEL1_MASK             (0x7F00U)
1544 #define TRGMUX_3_MSC_23_20_SEL1_SHIFT            (8U)
1545 #define TRGMUX_3_MSC_23_20_SEL1_WIDTH            (7U)
1546 #define TRGMUX_3_MSC_23_20_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_23_20_SEL1_SHIFT)) & TRGMUX_3_MSC_23_20_SEL1_MASK)
1547 
1548 #define TRGMUX_3_MSC_23_20_SEL2_MASK             (0x7F0000U)
1549 #define TRGMUX_3_MSC_23_20_SEL2_SHIFT            (16U)
1550 #define TRGMUX_3_MSC_23_20_SEL2_WIDTH            (7U)
1551 #define TRGMUX_3_MSC_23_20_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_23_20_SEL2_SHIFT)) & TRGMUX_3_MSC_23_20_SEL2_MASK)
1552 
1553 #define TRGMUX_3_MSC_23_20_SEL3_MASK             (0x7F000000U)
1554 #define TRGMUX_3_MSC_23_20_SEL3_SHIFT            (24U)
1555 #define TRGMUX_3_MSC_23_20_SEL3_WIDTH            (7U)
1556 #define TRGMUX_3_MSC_23_20_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_23_20_SEL3_SHIFT)) & TRGMUX_3_MSC_23_20_SEL3_MASK)
1557 
1558 #define TRGMUX_3_MSC_23_20_LK_MASK               (0x80000000U)
1559 #define TRGMUX_3_MSC_23_20_LK_SHIFT              (31U)
1560 #define TRGMUX_3_MSC_23_20_LK_WIDTH              (1U)
1561 #define TRGMUX_3_MSC_23_20_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_23_20_LK_SHIFT)) & TRGMUX_3_MSC_23_20_LK_MASK)
1562 /*! @} */
1563 
1564 /*! @name MSC_27_24 - TRGMUX MSC_27_24 */
1565 /*! @{ */
1566 
1567 #define TRGMUX_3_MSC_27_24_SEL0_MASK             (0x7FU)
1568 #define TRGMUX_3_MSC_27_24_SEL0_SHIFT            (0U)
1569 #define TRGMUX_3_MSC_27_24_SEL0_WIDTH            (7U)
1570 #define TRGMUX_3_MSC_27_24_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_27_24_SEL0_SHIFT)) & TRGMUX_3_MSC_27_24_SEL0_MASK)
1571 
1572 #define TRGMUX_3_MSC_27_24_SEL1_MASK             (0x7F00U)
1573 #define TRGMUX_3_MSC_27_24_SEL1_SHIFT            (8U)
1574 #define TRGMUX_3_MSC_27_24_SEL1_WIDTH            (7U)
1575 #define TRGMUX_3_MSC_27_24_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_27_24_SEL1_SHIFT)) & TRGMUX_3_MSC_27_24_SEL1_MASK)
1576 
1577 #define TRGMUX_3_MSC_27_24_SEL2_MASK             (0x7F0000U)
1578 #define TRGMUX_3_MSC_27_24_SEL2_SHIFT            (16U)
1579 #define TRGMUX_3_MSC_27_24_SEL2_WIDTH            (7U)
1580 #define TRGMUX_3_MSC_27_24_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_27_24_SEL2_SHIFT)) & TRGMUX_3_MSC_27_24_SEL2_MASK)
1581 
1582 #define TRGMUX_3_MSC_27_24_SEL3_MASK             (0x7F000000U)
1583 #define TRGMUX_3_MSC_27_24_SEL3_SHIFT            (24U)
1584 #define TRGMUX_3_MSC_27_24_SEL3_WIDTH            (7U)
1585 #define TRGMUX_3_MSC_27_24_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_27_24_SEL3_SHIFT)) & TRGMUX_3_MSC_27_24_SEL3_MASK)
1586 
1587 #define TRGMUX_3_MSC_27_24_LK_MASK               (0x80000000U)
1588 #define TRGMUX_3_MSC_27_24_LK_SHIFT              (31U)
1589 #define TRGMUX_3_MSC_27_24_LK_WIDTH              (1U)
1590 #define TRGMUX_3_MSC_27_24_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_27_24_LK_SHIFT)) & TRGMUX_3_MSC_27_24_LK_MASK)
1591 /*! @} */
1592 
1593 /*! @name MSC_31_28 - TRGMUX MSC_31_28 */
1594 /*! @{ */
1595 
1596 #define TRGMUX_3_MSC_31_28_SEL0_MASK             (0x7FU)
1597 #define TRGMUX_3_MSC_31_28_SEL0_SHIFT            (0U)
1598 #define TRGMUX_3_MSC_31_28_SEL0_WIDTH            (7U)
1599 #define TRGMUX_3_MSC_31_28_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_31_28_SEL0_SHIFT)) & TRGMUX_3_MSC_31_28_SEL0_MASK)
1600 
1601 #define TRGMUX_3_MSC_31_28_SEL1_MASK             (0x7F00U)
1602 #define TRGMUX_3_MSC_31_28_SEL1_SHIFT            (8U)
1603 #define TRGMUX_3_MSC_31_28_SEL1_WIDTH            (7U)
1604 #define TRGMUX_3_MSC_31_28_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_31_28_SEL1_SHIFT)) & TRGMUX_3_MSC_31_28_SEL1_MASK)
1605 
1606 #define TRGMUX_3_MSC_31_28_SEL2_MASK             (0x7F0000U)
1607 #define TRGMUX_3_MSC_31_28_SEL2_SHIFT            (16U)
1608 #define TRGMUX_3_MSC_31_28_SEL2_WIDTH            (7U)
1609 #define TRGMUX_3_MSC_31_28_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_31_28_SEL2_SHIFT)) & TRGMUX_3_MSC_31_28_SEL2_MASK)
1610 
1611 #define TRGMUX_3_MSC_31_28_SEL3_MASK             (0x7F000000U)
1612 #define TRGMUX_3_MSC_31_28_SEL3_SHIFT            (24U)
1613 #define TRGMUX_3_MSC_31_28_SEL3_WIDTH            (7U)
1614 #define TRGMUX_3_MSC_31_28_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_31_28_SEL3_SHIFT)) & TRGMUX_3_MSC_31_28_SEL3_MASK)
1615 
1616 #define TRGMUX_3_MSC_31_28_LK_MASK               (0x80000000U)
1617 #define TRGMUX_3_MSC_31_28_LK_SHIFT              (31U)
1618 #define TRGMUX_3_MSC_31_28_LK_WIDTH              (1U)
1619 #define TRGMUX_3_MSC_31_28_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_31_28_LK_SHIFT)) & TRGMUX_3_MSC_31_28_LK_MASK)
1620 /*! @} */
1621 
1622 /*! @name MSC_35_32 - TRGMUX MSC_35_32 */
1623 /*! @{ */
1624 
1625 #define TRGMUX_3_MSC_35_32_SEL0_MASK             (0x7FU)
1626 #define TRGMUX_3_MSC_35_32_SEL0_SHIFT            (0U)
1627 #define TRGMUX_3_MSC_35_32_SEL0_WIDTH            (7U)
1628 #define TRGMUX_3_MSC_35_32_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_35_32_SEL0_SHIFT)) & TRGMUX_3_MSC_35_32_SEL0_MASK)
1629 
1630 #define TRGMUX_3_MSC_35_32_SEL1_MASK             (0x7F00U)
1631 #define TRGMUX_3_MSC_35_32_SEL1_SHIFT            (8U)
1632 #define TRGMUX_3_MSC_35_32_SEL1_WIDTH            (7U)
1633 #define TRGMUX_3_MSC_35_32_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_35_32_SEL1_SHIFT)) & TRGMUX_3_MSC_35_32_SEL1_MASK)
1634 
1635 #define TRGMUX_3_MSC_35_32_SEL2_MASK             (0x7F0000U)
1636 #define TRGMUX_3_MSC_35_32_SEL2_SHIFT            (16U)
1637 #define TRGMUX_3_MSC_35_32_SEL2_WIDTH            (7U)
1638 #define TRGMUX_3_MSC_35_32_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_35_32_SEL2_SHIFT)) & TRGMUX_3_MSC_35_32_SEL2_MASK)
1639 
1640 #define TRGMUX_3_MSC_35_32_SEL3_MASK             (0x7F000000U)
1641 #define TRGMUX_3_MSC_35_32_SEL3_SHIFT            (24U)
1642 #define TRGMUX_3_MSC_35_32_SEL3_WIDTH            (7U)
1643 #define TRGMUX_3_MSC_35_32_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_35_32_SEL3_SHIFT)) & TRGMUX_3_MSC_35_32_SEL3_MASK)
1644 
1645 #define TRGMUX_3_MSC_35_32_LK_MASK               (0x80000000U)
1646 #define TRGMUX_3_MSC_35_32_LK_SHIFT              (31U)
1647 #define TRGMUX_3_MSC_35_32_LK_WIDTH              (1U)
1648 #define TRGMUX_3_MSC_35_32_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_35_32_LK_SHIFT)) & TRGMUX_3_MSC_35_32_LK_MASK)
1649 /*! @} */
1650 
1651 /*! @name MSC_39_36 - TRGMUX MSC_39_36 */
1652 /*! @{ */
1653 
1654 #define TRGMUX_3_MSC_39_36_SEL0_MASK             (0x7FU)
1655 #define TRGMUX_3_MSC_39_36_SEL0_SHIFT            (0U)
1656 #define TRGMUX_3_MSC_39_36_SEL0_WIDTH            (7U)
1657 #define TRGMUX_3_MSC_39_36_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_39_36_SEL0_SHIFT)) & TRGMUX_3_MSC_39_36_SEL0_MASK)
1658 
1659 #define TRGMUX_3_MSC_39_36_SEL1_MASK             (0x7F00U)
1660 #define TRGMUX_3_MSC_39_36_SEL1_SHIFT            (8U)
1661 #define TRGMUX_3_MSC_39_36_SEL1_WIDTH            (7U)
1662 #define TRGMUX_3_MSC_39_36_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_39_36_SEL1_SHIFT)) & TRGMUX_3_MSC_39_36_SEL1_MASK)
1663 
1664 #define TRGMUX_3_MSC_39_36_SEL2_MASK             (0x7F0000U)
1665 #define TRGMUX_3_MSC_39_36_SEL2_SHIFT            (16U)
1666 #define TRGMUX_3_MSC_39_36_SEL2_WIDTH            (7U)
1667 #define TRGMUX_3_MSC_39_36_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_39_36_SEL2_SHIFT)) & TRGMUX_3_MSC_39_36_SEL2_MASK)
1668 
1669 #define TRGMUX_3_MSC_39_36_SEL3_MASK             (0x7F000000U)
1670 #define TRGMUX_3_MSC_39_36_SEL3_SHIFT            (24U)
1671 #define TRGMUX_3_MSC_39_36_SEL3_WIDTH            (7U)
1672 #define TRGMUX_3_MSC_39_36_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_39_36_SEL3_SHIFT)) & TRGMUX_3_MSC_39_36_SEL3_MASK)
1673 
1674 #define TRGMUX_3_MSC_39_36_LK_MASK               (0x80000000U)
1675 #define TRGMUX_3_MSC_39_36_LK_SHIFT              (31U)
1676 #define TRGMUX_3_MSC_39_36_LK_WIDTH              (1U)
1677 #define TRGMUX_3_MSC_39_36_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_39_36_LK_SHIFT)) & TRGMUX_3_MSC_39_36_LK_MASK)
1678 /*! @} */
1679 
1680 /*! @name MSC_43_40 - TRGMUX MSC_43_40 */
1681 /*! @{ */
1682 
1683 #define TRGMUX_3_MSC_43_40_SEL0_MASK             (0x7FU)
1684 #define TRGMUX_3_MSC_43_40_SEL0_SHIFT            (0U)
1685 #define TRGMUX_3_MSC_43_40_SEL0_WIDTH            (7U)
1686 #define TRGMUX_3_MSC_43_40_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_43_40_SEL0_SHIFT)) & TRGMUX_3_MSC_43_40_SEL0_MASK)
1687 
1688 #define TRGMUX_3_MSC_43_40_SEL1_MASK             (0x7F00U)
1689 #define TRGMUX_3_MSC_43_40_SEL1_SHIFT            (8U)
1690 #define TRGMUX_3_MSC_43_40_SEL1_WIDTH            (7U)
1691 #define TRGMUX_3_MSC_43_40_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_43_40_SEL1_SHIFT)) & TRGMUX_3_MSC_43_40_SEL1_MASK)
1692 
1693 #define TRGMUX_3_MSC_43_40_SEL2_MASK             (0x7F0000U)
1694 #define TRGMUX_3_MSC_43_40_SEL2_SHIFT            (16U)
1695 #define TRGMUX_3_MSC_43_40_SEL2_WIDTH            (7U)
1696 #define TRGMUX_3_MSC_43_40_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_43_40_SEL2_SHIFT)) & TRGMUX_3_MSC_43_40_SEL2_MASK)
1697 
1698 #define TRGMUX_3_MSC_43_40_SEL3_MASK             (0x7F000000U)
1699 #define TRGMUX_3_MSC_43_40_SEL3_SHIFT            (24U)
1700 #define TRGMUX_3_MSC_43_40_SEL3_WIDTH            (7U)
1701 #define TRGMUX_3_MSC_43_40_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_43_40_SEL3_SHIFT)) & TRGMUX_3_MSC_43_40_SEL3_MASK)
1702 
1703 #define TRGMUX_3_MSC_43_40_LK_MASK               (0x80000000U)
1704 #define TRGMUX_3_MSC_43_40_LK_SHIFT              (31U)
1705 #define TRGMUX_3_MSC_43_40_LK_WIDTH              (1U)
1706 #define TRGMUX_3_MSC_43_40_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_43_40_LK_SHIFT)) & TRGMUX_3_MSC_43_40_LK_MASK)
1707 /*! @} */
1708 
1709 /*! @name MSC_47_44 - TRGMUX MSC_47_44 */
1710 /*! @{ */
1711 
1712 #define TRGMUX_3_MSC_47_44_SEL0_MASK             (0x7FU)
1713 #define TRGMUX_3_MSC_47_44_SEL0_SHIFT            (0U)
1714 #define TRGMUX_3_MSC_47_44_SEL0_WIDTH            (7U)
1715 #define TRGMUX_3_MSC_47_44_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_47_44_SEL0_SHIFT)) & TRGMUX_3_MSC_47_44_SEL0_MASK)
1716 
1717 #define TRGMUX_3_MSC_47_44_SEL1_MASK             (0x7F00U)
1718 #define TRGMUX_3_MSC_47_44_SEL1_SHIFT            (8U)
1719 #define TRGMUX_3_MSC_47_44_SEL1_WIDTH            (7U)
1720 #define TRGMUX_3_MSC_47_44_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_47_44_SEL1_SHIFT)) & TRGMUX_3_MSC_47_44_SEL1_MASK)
1721 
1722 #define TRGMUX_3_MSC_47_44_SEL2_MASK             (0x7F0000U)
1723 #define TRGMUX_3_MSC_47_44_SEL2_SHIFT            (16U)
1724 #define TRGMUX_3_MSC_47_44_SEL2_WIDTH            (7U)
1725 #define TRGMUX_3_MSC_47_44_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_47_44_SEL2_SHIFT)) & TRGMUX_3_MSC_47_44_SEL2_MASK)
1726 
1727 #define TRGMUX_3_MSC_47_44_SEL3_MASK             (0x7F000000U)
1728 #define TRGMUX_3_MSC_47_44_SEL3_SHIFT            (24U)
1729 #define TRGMUX_3_MSC_47_44_SEL3_WIDTH            (7U)
1730 #define TRGMUX_3_MSC_47_44_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_47_44_SEL3_SHIFT)) & TRGMUX_3_MSC_47_44_SEL3_MASK)
1731 
1732 #define TRGMUX_3_MSC_47_44_LK_MASK               (0x80000000U)
1733 #define TRGMUX_3_MSC_47_44_LK_SHIFT              (31U)
1734 #define TRGMUX_3_MSC_47_44_LK_WIDTH              (1U)
1735 #define TRGMUX_3_MSC_47_44_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_47_44_LK_SHIFT)) & TRGMUX_3_MSC_47_44_LK_MASK)
1736 /*! @} */
1737 
1738 /*! @name MSC_51_48 - TRGMUX MSC_51_48 */
1739 /*! @{ */
1740 
1741 #define TRGMUX_3_MSC_51_48_SEL0_MASK             (0x7FU)
1742 #define TRGMUX_3_MSC_51_48_SEL0_SHIFT            (0U)
1743 #define TRGMUX_3_MSC_51_48_SEL0_WIDTH            (7U)
1744 #define TRGMUX_3_MSC_51_48_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_51_48_SEL0_SHIFT)) & TRGMUX_3_MSC_51_48_SEL0_MASK)
1745 
1746 #define TRGMUX_3_MSC_51_48_SEL1_MASK             (0x7F00U)
1747 #define TRGMUX_3_MSC_51_48_SEL1_SHIFT            (8U)
1748 #define TRGMUX_3_MSC_51_48_SEL1_WIDTH            (7U)
1749 #define TRGMUX_3_MSC_51_48_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_51_48_SEL1_SHIFT)) & TRGMUX_3_MSC_51_48_SEL1_MASK)
1750 
1751 #define TRGMUX_3_MSC_51_48_SEL2_MASK             (0x7F0000U)
1752 #define TRGMUX_3_MSC_51_48_SEL2_SHIFT            (16U)
1753 #define TRGMUX_3_MSC_51_48_SEL2_WIDTH            (7U)
1754 #define TRGMUX_3_MSC_51_48_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_51_48_SEL2_SHIFT)) & TRGMUX_3_MSC_51_48_SEL2_MASK)
1755 
1756 #define TRGMUX_3_MSC_51_48_SEL3_MASK             (0x7F000000U)
1757 #define TRGMUX_3_MSC_51_48_SEL3_SHIFT            (24U)
1758 #define TRGMUX_3_MSC_51_48_SEL3_WIDTH            (7U)
1759 #define TRGMUX_3_MSC_51_48_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_51_48_SEL3_SHIFT)) & TRGMUX_3_MSC_51_48_SEL3_MASK)
1760 
1761 #define TRGMUX_3_MSC_51_48_LK_MASK               (0x80000000U)
1762 #define TRGMUX_3_MSC_51_48_LK_SHIFT              (31U)
1763 #define TRGMUX_3_MSC_51_48_LK_WIDTH              (1U)
1764 #define TRGMUX_3_MSC_51_48_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_51_48_LK_SHIFT)) & TRGMUX_3_MSC_51_48_LK_MASK)
1765 /*! @} */
1766 
1767 /*! @name MSC_55_52 - TRGMUX MSC_55_52 */
1768 /*! @{ */
1769 
1770 #define TRGMUX_3_MSC_55_52_SEL0_MASK             (0x7FU)
1771 #define TRGMUX_3_MSC_55_52_SEL0_SHIFT            (0U)
1772 #define TRGMUX_3_MSC_55_52_SEL0_WIDTH            (7U)
1773 #define TRGMUX_3_MSC_55_52_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_55_52_SEL0_SHIFT)) & TRGMUX_3_MSC_55_52_SEL0_MASK)
1774 
1775 #define TRGMUX_3_MSC_55_52_SEL1_MASK             (0x7F00U)
1776 #define TRGMUX_3_MSC_55_52_SEL1_SHIFT            (8U)
1777 #define TRGMUX_3_MSC_55_52_SEL1_WIDTH            (7U)
1778 #define TRGMUX_3_MSC_55_52_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_55_52_SEL1_SHIFT)) & TRGMUX_3_MSC_55_52_SEL1_MASK)
1779 
1780 #define TRGMUX_3_MSC_55_52_SEL2_MASK             (0x7F0000U)
1781 #define TRGMUX_3_MSC_55_52_SEL2_SHIFT            (16U)
1782 #define TRGMUX_3_MSC_55_52_SEL2_WIDTH            (7U)
1783 #define TRGMUX_3_MSC_55_52_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_55_52_SEL2_SHIFT)) & TRGMUX_3_MSC_55_52_SEL2_MASK)
1784 
1785 #define TRGMUX_3_MSC_55_52_SEL3_MASK             (0x7F000000U)
1786 #define TRGMUX_3_MSC_55_52_SEL3_SHIFT            (24U)
1787 #define TRGMUX_3_MSC_55_52_SEL3_WIDTH            (7U)
1788 #define TRGMUX_3_MSC_55_52_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_55_52_SEL3_SHIFT)) & TRGMUX_3_MSC_55_52_SEL3_MASK)
1789 
1790 #define TRGMUX_3_MSC_55_52_LK_MASK               (0x80000000U)
1791 #define TRGMUX_3_MSC_55_52_LK_SHIFT              (31U)
1792 #define TRGMUX_3_MSC_55_52_LK_WIDTH              (1U)
1793 #define TRGMUX_3_MSC_55_52_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_55_52_LK_SHIFT)) & TRGMUX_3_MSC_55_52_LK_MASK)
1794 /*! @} */
1795 
1796 /*! @name MSC_59_56 - TRGMUX MSC_59_56 */
1797 /*! @{ */
1798 
1799 #define TRGMUX_3_MSC_59_56_SEL0_MASK             (0x7FU)
1800 #define TRGMUX_3_MSC_59_56_SEL0_SHIFT            (0U)
1801 #define TRGMUX_3_MSC_59_56_SEL0_WIDTH            (7U)
1802 #define TRGMUX_3_MSC_59_56_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_59_56_SEL0_SHIFT)) & TRGMUX_3_MSC_59_56_SEL0_MASK)
1803 
1804 #define TRGMUX_3_MSC_59_56_SEL1_MASK             (0x7F00U)
1805 #define TRGMUX_3_MSC_59_56_SEL1_SHIFT            (8U)
1806 #define TRGMUX_3_MSC_59_56_SEL1_WIDTH            (7U)
1807 #define TRGMUX_3_MSC_59_56_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_59_56_SEL1_SHIFT)) & TRGMUX_3_MSC_59_56_SEL1_MASK)
1808 
1809 #define TRGMUX_3_MSC_59_56_SEL2_MASK             (0x7F0000U)
1810 #define TRGMUX_3_MSC_59_56_SEL2_SHIFT            (16U)
1811 #define TRGMUX_3_MSC_59_56_SEL2_WIDTH            (7U)
1812 #define TRGMUX_3_MSC_59_56_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_59_56_SEL2_SHIFT)) & TRGMUX_3_MSC_59_56_SEL2_MASK)
1813 
1814 #define TRGMUX_3_MSC_59_56_SEL3_MASK             (0x7F000000U)
1815 #define TRGMUX_3_MSC_59_56_SEL3_SHIFT            (24U)
1816 #define TRGMUX_3_MSC_59_56_SEL3_WIDTH            (7U)
1817 #define TRGMUX_3_MSC_59_56_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_59_56_SEL3_SHIFT)) & TRGMUX_3_MSC_59_56_SEL3_MASK)
1818 
1819 #define TRGMUX_3_MSC_59_56_LK_MASK               (0x80000000U)
1820 #define TRGMUX_3_MSC_59_56_LK_SHIFT              (31U)
1821 #define TRGMUX_3_MSC_59_56_LK_WIDTH              (1U)
1822 #define TRGMUX_3_MSC_59_56_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_59_56_LK_SHIFT)) & TRGMUX_3_MSC_59_56_LK_MASK)
1823 /*! @} */
1824 
1825 /*! @name MSC_63_60 - TRGMUX MSC_63_60 */
1826 /*! @{ */
1827 
1828 #define TRGMUX_3_MSC_63_60_SEL0_MASK             (0x7FU)
1829 #define TRGMUX_3_MSC_63_60_SEL0_SHIFT            (0U)
1830 #define TRGMUX_3_MSC_63_60_SEL0_WIDTH            (7U)
1831 #define TRGMUX_3_MSC_63_60_SEL0(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_63_60_SEL0_SHIFT)) & TRGMUX_3_MSC_63_60_SEL0_MASK)
1832 
1833 #define TRGMUX_3_MSC_63_60_SEL1_MASK             (0x7F00U)
1834 #define TRGMUX_3_MSC_63_60_SEL1_SHIFT            (8U)
1835 #define TRGMUX_3_MSC_63_60_SEL1_WIDTH            (7U)
1836 #define TRGMUX_3_MSC_63_60_SEL1(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_63_60_SEL1_SHIFT)) & TRGMUX_3_MSC_63_60_SEL1_MASK)
1837 
1838 #define TRGMUX_3_MSC_63_60_SEL2_MASK             (0x7F0000U)
1839 #define TRGMUX_3_MSC_63_60_SEL2_SHIFT            (16U)
1840 #define TRGMUX_3_MSC_63_60_SEL2_WIDTH            (7U)
1841 #define TRGMUX_3_MSC_63_60_SEL2(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_63_60_SEL2_SHIFT)) & TRGMUX_3_MSC_63_60_SEL2_MASK)
1842 
1843 #define TRGMUX_3_MSC_63_60_SEL3_MASK             (0x7F000000U)
1844 #define TRGMUX_3_MSC_63_60_SEL3_SHIFT            (24U)
1845 #define TRGMUX_3_MSC_63_60_SEL3_WIDTH            (7U)
1846 #define TRGMUX_3_MSC_63_60_SEL3(x)               (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_63_60_SEL3_SHIFT)) & TRGMUX_3_MSC_63_60_SEL3_MASK)
1847 
1848 #define TRGMUX_3_MSC_63_60_LK_MASK               (0x80000000U)
1849 #define TRGMUX_3_MSC_63_60_LK_SHIFT              (31U)
1850 #define TRGMUX_3_MSC_63_60_LK_WIDTH              (1U)
1851 #define TRGMUX_3_MSC_63_60_LK(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_MSC_63_60_LK_SHIFT)) & TRGMUX_3_MSC_63_60_LK_MASK)
1852 /*! @} */
1853 
1854 /*! @name CTU_3_0 - TRGMUX CTU_3_0 */
1855 /*! @{ */
1856 
1857 #define TRGMUX_3_CTU_3_0_SEL0_MASK               (0x7FU)
1858 #define TRGMUX_3_CTU_3_0_SEL0_SHIFT              (0U)
1859 #define TRGMUX_3_CTU_3_0_SEL0_WIDTH              (7U)
1860 #define TRGMUX_3_CTU_3_0_SEL0(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_CTU_3_0_SEL0_SHIFT)) & TRGMUX_3_CTU_3_0_SEL0_MASK)
1861 
1862 #define TRGMUX_3_CTU_3_0_SEL1_MASK               (0x7F00U)
1863 #define TRGMUX_3_CTU_3_0_SEL1_SHIFT              (8U)
1864 #define TRGMUX_3_CTU_3_0_SEL1_WIDTH              (7U)
1865 #define TRGMUX_3_CTU_3_0_SEL1(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_CTU_3_0_SEL1_SHIFT)) & TRGMUX_3_CTU_3_0_SEL1_MASK)
1866 
1867 #define TRGMUX_3_CTU_3_0_SEL2_MASK               (0x7F0000U)
1868 #define TRGMUX_3_CTU_3_0_SEL2_SHIFT              (16U)
1869 #define TRGMUX_3_CTU_3_0_SEL2_WIDTH              (7U)
1870 #define TRGMUX_3_CTU_3_0_SEL2(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_CTU_3_0_SEL2_SHIFT)) & TRGMUX_3_CTU_3_0_SEL2_MASK)
1871 
1872 #define TRGMUX_3_CTU_3_0_SEL3_MASK               (0x7F000000U)
1873 #define TRGMUX_3_CTU_3_0_SEL3_SHIFT              (24U)
1874 #define TRGMUX_3_CTU_3_0_SEL3_WIDTH              (7U)
1875 #define TRGMUX_3_CTU_3_0_SEL3(x)                 (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_CTU_3_0_SEL3_SHIFT)) & TRGMUX_3_CTU_3_0_SEL3_MASK)
1876 
1877 #define TRGMUX_3_CTU_3_0_LK_MASK                 (0x80000000U)
1878 #define TRGMUX_3_CTU_3_0_LK_SHIFT                (31U)
1879 #define TRGMUX_3_CTU_3_0_LK_WIDTH                (1U)
1880 #define TRGMUX_3_CTU_3_0_LK(x)                   (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_CTU_3_0_LK_SHIFT)) & TRGMUX_3_CTU_3_0_LK_MASK)
1881 /*! @} */
1882 
1883 /*! @name SINC_3_0 - TRGMUX SINC_3_0 */
1884 /*! @{ */
1885 
1886 #define TRGMUX_3_SINC_3_0_SEL0_MASK              (0x7FU)
1887 #define TRGMUX_3_SINC_3_0_SEL0_SHIFT             (0U)
1888 #define TRGMUX_3_SINC_3_0_SEL0_WIDTH             (7U)
1889 #define TRGMUX_3_SINC_3_0_SEL0(x)                (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_SINC_3_0_SEL0_SHIFT)) & TRGMUX_3_SINC_3_0_SEL0_MASK)
1890 
1891 #define TRGMUX_3_SINC_3_0_SEL1_MASK              (0x7F00U)
1892 #define TRGMUX_3_SINC_3_0_SEL1_SHIFT             (8U)
1893 #define TRGMUX_3_SINC_3_0_SEL1_WIDTH             (7U)
1894 #define TRGMUX_3_SINC_3_0_SEL1(x)                (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_SINC_3_0_SEL1_SHIFT)) & TRGMUX_3_SINC_3_0_SEL1_MASK)
1895 
1896 #define TRGMUX_3_SINC_3_0_SEL2_MASK              (0x7F0000U)
1897 #define TRGMUX_3_SINC_3_0_SEL2_SHIFT             (16U)
1898 #define TRGMUX_3_SINC_3_0_SEL2_WIDTH             (7U)
1899 #define TRGMUX_3_SINC_3_0_SEL2(x)                (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_SINC_3_0_SEL2_SHIFT)) & TRGMUX_3_SINC_3_0_SEL2_MASK)
1900 
1901 #define TRGMUX_3_SINC_3_0_SEL3_MASK              (0x7F000000U)
1902 #define TRGMUX_3_SINC_3_0_SEL3_SHIFT             (24U)
1903 #define TRGMUX_3_SINC_3_0_SEL3_WIDTH             (7U)
1904 #define TRGMUX_3_SINC_3_0_SEL3(x)                (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_SINC_3_0_SEL3_SHIFT)) & TRGMUX_3_SINC_3_0_SEL3_MASK)
1905 
1906 #define TRGMUX_3_SINC_3_0_LK_MASK                (0x80000000U)
1907 #define TRGMUX_3_SINC_3_0_LK_SHIFT               (31U)
1908 #define TRGMUX_3_SINC_3_0_LK_WIDTH               (1U)
1909 #define TRGMUX_3_SINC_3_0_LK(x)                  (((uint32_t)(((uint32_t)(x)) << TRGMUX_3_SINC_3_0_LK_SHIFT)) & TRGMUX_3_SINC_3_0_LK_MASK)
1910 /*! @} */
1911 
1912 /*!
1913  * @}
1914  */ /* end of group TRGMUX_3_Register_Masks */
1915 
1916 /*!
1917  * @}
1918  */ /* end of group TRGMUX_3_Peripheral_Access_Layer */
1919 
1920 #endif  /* #if !defined(S32Z2_TRGMUX_3_H_) */
1921