1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_TIMERS.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_TIMERS 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_TIMERS_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_TIMERS_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- TIMERS Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup TIMERS_Peripheral_Access_Layer TIMERS Peripheral Access Layer 68 * @{ 69 */ 70 71 /** TIMERS - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t TIMER0_CFG; /**< TIMER0 CFG, offset: 0x0 */ 74 __IO uint32_t TIMER0_EW; /**< TIMER0 EW, offset: 0x4 */ 75 __I uint32_t TIMER0_CC; /**< TIMER0 CC, offset: 0x8 */ 76 __IO uint32_t TIMER0_SC; /**< TIMER0 SC, offset: 0xC */ 77 __IO uint32_t TIMER1_CFG; /**< TIMER1 CFG, offset: 0x10 */ 78 __IO uint32_t TIMER1_EW; /**< TIMER1 EW, offset: 0x14 */ 79 __I uint32_t TIMER1_CC; /**< TIMER1 CC, offset: 0x18 */ 80 __IO uint32_t TIMER1_SC; /**< TIMER1 SC, offset: 0x1C */ 81 __IO uint32_t TIMER2_CFG; /**< TIMER2 CFG, offset: 0x20 */ 82 __IO uint32_t TIMER2_EW; /**< TIMER2 EW, offset: 0x24 */ 83 __I uint32_t TIMER2_CC; /**< TIMER2 CC, offset: 0x28 */ 84 __IO uint32_t TIMER2_SC; /**< TIMER2 SC, offset: 0x2C */ 85 __IO uint32_t TIMER3_CFG; /**< TIMER3 CFG, offset: 0x30 */ 86 __IO uint32_t TIMER3_EW; /**< TIMER3 EW, offset: 0x34 */ 87 __I uint32_t TIMER3_CC; /**< TIMER3 CC, offset: 0x38 */ 88 __IO uint32_t TIMER3_SC; /**< TIMER3 SC, offset: 0x3C */ 89 } TIMERS_Type, *TIMERS_MemMapPtr; 90 91 /** Number of instances of the TIMERS module. */ 92 #define TIMERS_INSTANCE_COUNT (1u) 93 94 /* TIMERS - Peripheral instance base addresses */ 95 /** Peripheral CEVA_SPF2__TIMERS base address */ 96 #define IP_CEVA_SPF2__TIMERS_BASE (0x24402000u) 97 /** Peripheral CEVA_SPF2__TIMERS base pointer */ 98 #define IP_CEVA_SPF2__TIMERS ((TIMERS_Type *)IP_CEVA_SPF2__TIMERS_BASE) 99 /** Array initializer of TIMERS peripheral base addresses */ 100 #define IP_TIMERS_BASE_ADDRS { IP_CEVA_SPF2__TIMERS_BASE } 101 /** Array initializer of TIMERS peripheral base pointers */ 102 #define IP_TIMERS_BASE_PTRS { IP_CEVA_SPF2__TIMERS } 103 104 /* ---------------------------------------------------------------------------- 105 -- TIMERS Register Masks 106 ---------------------------------------------------------------------------- */ 107 108 /*! 109 * @addtogroup TIMERS_Register_Masks TIMERS Register Masks 110 * @{ 111 */ 112 113 /*! @name TIMER0_CFG - TIMER0 CFG */ 114 /*! @{ */ 115 116 #define TIMERS_TIMER0_CFG_TS_MASK (0x3U) 117 #define TIMERS_TIMER0_CFG_TS_SHIFT (0U) 118 #define TIMERS_TIMER0_CFG_TS_WIDTH (2U) 119 #define TIMERS_TIMER0_CFG_TS(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER0_CFG_TS_SHIFT)) & TIMERS_TIMER0_CFG_TS_MASK) 120 121 #define TIMERS_TIMER0_CFG_CM_MASK (0x1CU) 122 #define TIMERS_TIMER0_CFG_CM_SHIFT (2U) 123 #define TIMERS_TIMER0_CFG_CM_WIDTH (3U) 124 #define TIMERS_TIMER0_CFG_CM(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER0_CFG_CM_SHIFT)) & TIMERS_TIMER0_CFG_CM_MASK) 125 126 #define TIMERS_TIMER0_CFG_ES_MASK (0x20U) 127 #define TIMERS_TIMER0_CFG_ES_SHIFT (5U) 128 #define TIMERS_TIMER0_CFG_ES_WIDTH (1U) 129 #define TIMERS_TIMER0_CFG_ES(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER0_CFG_ES_SHIFT)) & TIMERS_TIMER0_CFG_ES_MASK) 130 131 #define TIMERS_TIMER0_CFG_TP_MASK (0x40U) 132 #define TIMERS_TIMER0_CFG_TP_SHIFT (6U) 133 #define TIMERS_TIMER0_CFG_TP_WIDTH (1U) 134 #define TIMERS_TIMER0_CFG_TP(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER0_CFG_TP_SHIFT)) & TIMERS_TIMER0_CFG_TP_MASK) 135 136 #define TIMERS_TIMER0_CFG_TM_MASK (0x180U) 137 #define TIMERS_TIMER0_CFG_TM_SHIFT (7U) 138 #define TIMERS_TIMER0_CFG_TM_WIDTH (2U) 139 #define TIMERS_TIMER0_CFG_TM(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER0_CFG_TM_SHIFT)) & TIMERS_TIMER0_CFG_TM_MASK) 140 141 #define TIMERS_TIMER0_CFG_CAS_MASK (0x400U) 142 #define TIMERS_TIMER0_CFG_CAS_SHIFT (10U) 143 #define TIMERS_TIMER0_CFG_CAS_WIDTH (1U) 144 #define TIMERS_TIMER0_CFG_CAS(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER0_CFG_CAS_SHIFT)) & TIMERS_TIMER0_CFG_CAS_MASK) 145 146 #define TIMERS_TIMER0_CFG_RES_MASK (0x10000U) 147 #define TIMERS_TIMER0_CFG_RES_SHIFT (16U) 148 #define TIMERS_TIMER0_CFG_RES_WIDTH (1U) 149 #define TIMERS_TIMER0_CFG_RES(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER0_CFG_RES_SHIFT)) & TIMERS_TIMER0_CFG_RES_MASK) 150 151 #define TIMERS_TIMER0_CFG_PC_MASK (0x20000U) 152 #define TIMERS_TIMER0_CFG_PC_SHIFT (17U) 153 #define TIMERS_TIMER0_CFG_PC_WIDTH (1U) 154 #define TIMERS_TIMER0_CFG_PC(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER0_CFG_PC_SHIFT)) & TIMERS_TIMER0_CFG_PC_MASK) 155 156 #define TIMERS_TIMER0_CFG_CT_MASK (0x40000U) 157 #define TIMERS_TIMER0_CFG_CT_SHIFT (18U) 158 #define TIMERS_TIMER0_CFG_CT_WIDTH (1U) 159 #define TIMERS_TIMER0_CFG_CT(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER0_CFG_CT_SHIFT)) & TIMERS_TIMER0_CFG_CT_MASK) 160 161 #define TIMERS_TIMER0_CFG_RU_MASK (0x80000U) 162 #define TIMERS_TIMER0_CFG_RU_SHIFT (19U) 163 #define TIMERS_TIMER0_CFG_RU_WIDTH (1U) 164 #define TIMERS_TIMER0_CFG_RU(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER0_CFG_RU_SHIFT)) & TIMERS_TIMER0_CFG_RU_MASK) 165 166 #define TIMERS_TIMER0_CFG_BPEN_MASK (0x100000U) 167 #define TIMERS_TIMER0_CFG_BPEN_SHIFT (20U) 168 #define TIMERS_TIMER0_CFG_BPEN_WIDTH (1U) 169 #define TIMERS_TIMER0_CFG_BPEN(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER0_CFG_BPEN_SHIFT)) & TIMERS_TIMER0_CFG_BPEN_MASK) 170 /*! @} */ 171 172 /*! @name TIMER0_EW - TIMER0 EW */ 173 /*! @{ */ 174 175 #define TIMERS_TIMER0_EW_EW_MASK (0x1U) 176 #define TIMERS_TIMER0_EW_EW_SHIFT (0U) 177 #define TIMERS_TIMER0_EW_EW_WIDTH (1U) 178 #define TIMERS_TIMER0_EW_EW(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER0_EW_EW_SHIFT)) & TIMERS_TIMER0_EW_EW_MASK) 179 /*! @} */ 180 181 /*! @name TIMER0_CC - TIMER0 CC */ 182 /*! @{ */ 183 184 #define TIMERS_TIMER0_CC_CC_MASK (0xFFFFFFFFU) 185 #define TIMERS_TIMER0_CC_CC_SHIFT (0U) 186 #define TIMERS_TIMER0_CC_CC_WIDTH (32U) 187 #define TIMERS_TIMER0_CC_CC(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER0_CC_CC_SHIFT)) & TIMERS_TIMER0_CC_CC_MASK) 188 /*! @} */ 189 190 /*! @name TIMER0_SC - TIMER0 SC */ 191 /*! @{ */ 192 193 #define TIMERS_TIMER0_SC_SC_MASK (0xFFFFFFFFU) 194 #define TIMERS_TIMER0_SC_SC_SHIFT (0U) 195 #define TIMERS_TIMER0_SC_SC_WIDTH (32U) 196 #define TIMERS_TIMER0_SC_SC(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER0_SC_SC_SHIFT)) & TIMERS_TIMER0_SC_SC_MASK) 197 /*! @} */ 198 199 /*! @name TIMER1_CFG - TIMER1 CFG */ 200 /*! @{ */ 201 202 #define TIMERS_TIMER1_CFG_TS_MASK (0x3U) 203 #define TIMERS_TIMER1_CFG_TS_SHIFT (0U) 204 #define TIMERS_TIMER1_CFG_TS_WIDTH (2U) 205 #define TIMERS_TIMER1_CFG_TS(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER1_CFG_TS_SHIFT)) & TIMERS_TIMER1_CFG_TS_MASK) 206 207 #define TIMERS_TIMER1_CFG_CM_MASK (0x1CU) 208 #define TIMERS_TIMER1_CFG_CM_SHIFT (2U) 209 #define TIMERS_TIMER1_CFG_CM_WIDTH (3U) 210 #define TIMERS_TIMER1_CFG_CM(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER1_CFG_CM_SHIFT)) & TIMERS_TIMER1_CFG_CM_MASK) 211 212 #define TIMERS_TIMER1_CFG_ES_MASK (0x20U) 213 #define TIMERS_TIMER1_CFG_ES_SHIFT (5U) 214 #define TIMERS_TIMER1_CFG_ES_WIDTH (1U) 215 #define TIMERS_TIMER1_CFG_ES(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER1_CFG_ES_SHIFT)) & TIMERS_TIMER1_CFG_ES_MASK) 216 217 #define TIMERS_TIMER1_CFG_RES_MASK (0x10000U) 218 #define TIMERS_TIMER1_CFG_RES_SHIFT (16U) 219 #define TIMERS_TIMER1_CFG_RES_WIDTH (1U) 220 #define TIMERS_TIMER1_CFG_RES(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER1_CFG_RES_SHIFT)) & TIMERS_TIMER1_CFG_RES_MASK) 221 222 #define TIMERS_TIMER1_CFG_PC_MASK (0x20000U) 223 #define TIMERS_TIMER1_CFG_PC_SHIFT (17U) 224 #define TIMERS_TIMER1_CFG_PC_WIDTH (1U) 225 #define TIMERS_TIMER1_CFG_PC(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER1_CFG_PC_SHIFT)) & TIMERS_TIMER1_CFG_PC_MASK) 226 227 #define TIMERS_TIMER1_CFG_RU_MASK (0x80000U) 228 #define TIMERS_TIMER1_CFG_RU_SHIFT (19U) 229 #define TIMERS_TIMER1_CFG_RU_WIDTH (1U) 230 #define TIMERS_TIMER1_CFG_RU(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER1_CFG_RU_SHIFT)) & TIMERS_TIMER1_CFG_RU_MASK) 231 232 #define TIMERS_TIMER1_CFG_BPEN_MASK (0x100000U) 233 #define TIMERS_TIMER1_CFG_BPEN_SHIFT (20U) 234 #define TIMERS_TIMER1_CFG_BPEN_WIDTH (1U) 235 #define TIMERS_TIMER1_CFG_BPEN(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER1_CFG_BPEN_SHIFT)) & TIMERS_TIMER1_CFG_BPEN_MASK) 236 /*! @} */ 237 238 /*! @name TIMER1_EW - TIMER1 EW */ 239 /*! @{ */ 240 241 #define TIMERS_TIMER1_EW_EW_MASK (0x1U) 242 #define TIMERS_TIMER1_EW_EW_SHIFT (0U) 243 #define TIMERS_TIMER1_EW_EW_WIDTH (1U) 244 #define TIMERS_TIMER1_EW_EW(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER1_EW_EW_SHIFT)) & TIMERS_TIMER1_EW_EW_MASK) 245 /*! @} */ 246 247 /*! @name TIMER1_CC - TIMER1 CC */ 248 /*! @{ */ 249 250 #define TIMERS_TIMER1_CC_CC_MASK (0xFFFFFFFFU) 251 #define TIMERS_TIMER1_CC_CC_SHIFT (0U) 252 #define TIMERS_TIMER1_CC_CC_WIDTH (32U) 253 #define TIMERS_TIMER1_CC_CC(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER1_CC_CC_SHIFT)) & TIMERS_TIMER1_CC_CC_MASK) 254 /*! @} */ 255 256 /*! @name TIMER1_SC - TIMER1 SC */ 257 /*! @{ */ 258 259 #define TIMERS_TIMER1_SC_SC_MASK (0xFFFFFFFFU) 260 #define TIMERS_TIMER1_SC_SC_SHIFT (0U) 261 #define TIMERS_TIMER1_SC_SC_WIDTH (32U) 262 #define TIMERS_TIMER1_SC_SC(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER1_SC_SC_SHIFT)) & TIMERS_TIMER1_SC_SC_MASK) 263 /*! @} */ 264 265 /*! @name TIMER2_CFG - TIMER2 CFG */ 266 /*! @{ */ 267 268 #define TIMERS_TIMER2_CFG_TS_MASK (0x3U) 269 #define TIMERS_TIMER2_CFG_TS_SHIFT (0U) 270 #define TIMERS_TIMER2_CFG_TS_WIDTH (2U) 271 #define TIMERS_TIMER2_CFG_TS(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER2_CFG_TS_SHIFT)) & TIMERS_TIMER2_CFG_TS_MASK) 272 273 #define TIMERS_TIMER2_CFG_CM_MASK (0x1CU) 274 #define TIMERS_TIMER2_CFG_CM_SHIFT (2U) 275 #define TIMERS_TIMER2_CFG_CM_WIDTH (3U) 276 #define TIMERS_TIMER2_CFG_CM(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER2_CFG_CM_SHIFT)) & TIMERS_TIMER2_CFG_CM_MASK) 277 278 #define TIMERS_TIMER2_CFG_ES_MASK (0x20U) 279 #define TIMERS_TIMER2_CFG_ES_SHIFT (5U) 280 #define TIMERS_TIMER2_CFG_ES_WIDTH (1U) 281 #define TIMERS_TIMER2_CFG_ES(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER2_CFG_ES_SHIFT)) & TIMERS_TIMER2_CFG_ES_MASK) 282 283 #define TIMERS_TIMER2_CFG_CAS_MASK (0x400U) 284 #define TIMERS_TIMER2_CFG_CAS_SHIFT (10U) 285 #define TIMERS_TIMER2_CFG_CAS_WIDTH (1U) 286 #define TIMERS_TIMER2_CFG_CAS(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER2_CFG_CAS_SHIFT)) & TIMERS_TIMER2_CFG_CAS_MASK) 287 288 #define TIMERS_TIMER2_CFG_RES_MASK (0x10000U) 289 #define TIMERS_TIMER2_CFG_RES_SHIFT (16U) 290 #define TIMERS_TIMER2_CFG_RES_WIDTH (1U) 291 #define TIMERS_TIMER2_CFG_RES(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER2_CFG_RES_SHIFT)) & TIMERS_TIMER2_CFG_RES_MASK) 292 293 #define TIMERS_TIMER2_CFG_PC_MASK (0x20000U) 294 #define TIMERS_TIMER2_CFG_PC_SHIFT (17U) 295 #define TIMERS_TIMER2_CFG_PC_WIDTH (1U) 296 #define TIMERS_TIMER2_CFG_PC(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER2_CFG_PC_SHIFT)) & TIMERS_TIMER2_CFG_PC_MASK) 297 298 #define TIMERS_TIMER2_CFG_RU_MASK (0x80000U) 299 #define TIMERS_TIMER2_CFG_RU_SHIFT (19U) 300 #define TIMERS_TIMER2_CFG_RU_WIDTH (1U) 301 #define TIMERS_TIMER2_CFG_RU(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER2_CFG_RU_SHIFT)) & TIMERS_TIMER2_CFG_RU_MASK) 302 303 #define TIMERS_TIMER2_CFG_BPEN_MASK (0x100000U) 304 #define TIMERS_TIMER2_CFG_BPEN_SHIFT (20U) 305 #define TIMERS_TIMER2_CFG_BPEN_WIDTH (1U) 306 #define TIMERS_TIMER2_CFG_BPEN(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER2_CFG_BPEN_SHIFT)) & TIMERS_TIMER2_CFG_BPEN_MASK) 307 /*! @} */ 308 309 /*! @name TIMER2_EW - TIMER2 EW */ 310 /*! @{ */ 311 312 #define TIMERS_TIMER2_EW_EW_MASK (0x1U) 313 #define TIMERS_TIMER2_EW_EW_SHIFT (0U) 314 #define TIMERS_TIMER2_EW_EW_WIDTH (1U) 315 #define TIMERS_TIMER2_EW_EW(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER2_EW_EW_SHIFT)) & TIMERS_TIMER2_EW_EW_MASK) 316 /*! @} */ 317 318 /*! @name TIMER2_CC - TIMER2 CC */ 319 /*! @{ */ 320 321 #define TIMERS_TIMER2_CC_CC_MASK (0xFFFFFFFFU) 322 #define TIMERS_TIMER2_CC_CC_SHIFT (0U) 323 #define TIMERS_TIMER2_CC_CC_WIDTH (32U) 324 #define TIMERS_TIMER2_CC_CC(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER2_CC_CC_SHIFT)) & TIMERS_TIMER2_CC_CC_MASK) 325 /*! @} */ 326 327 /*! @name TIMER2_SC - TIMER2 SC */ 328 /*! @{ */ 329 330 #define TIMERS_TIMER2_SC_SC_MASK (0xFFFFFFFFU) 331 #define TIMERS_TIMER2_SC_SC_SHIFT (0U) 332 #define TIMERS_TIMER2_SC_SC_WIDTH (32U) 333 #define TIMERS_TIMER2_SC_SC(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER2_SC_SC_SHIFT)) & TIMERS_TIMER2_SC_SC_MASK) 334 /*! @} */ 335 336 /*! @name TIMER3_CFG - TIMER3 CFG */ 337 /*! @{ */ 338 339 #define TIMERS_TIMER3_CFG_TS_MASK (0x3U) 340 #define TIMERS_TIMER3_CFG_TS_SHIFT (0U) 341 #define TIMERS_TIMER3_CFG_TS_WIDTH (2U) 342 #define TIMERS_TIMER3_CFG_TS(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER3_CFG_TS_SHIFT)) & TIMERS_TIMER3_CFG_TS_MASK) 343 344 #define TIMERS_TIMER3_CFG_CM_MASK (0x1CU) 345 #define TIMERS_TIMER3_CFG_CM_SHIFT (2U) 346 #define TIMERS_TIMER3_CFG_CM_WIDTH (3U) 347 #define TIMERS_TIMER3_CFG_CM(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER3_CFG_CM_SHIFT)) & TIMERS_TIMER3_CFG_CM_MASK) 348 349 #define TIMERS_TIMER3_CFG_ES_MASK (0x20U) 350 #define TIMERS_TIMER3_CFG_ES_SHIFT (5U) 351 #define TIMERS_TIMER3_CFG_ES_WIDTH (1U) 352 #define TIMERS_TIMER3_CFG_ES(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER3_CFG_ES_SHIFT)) & TIMERS_TIMER3_CFG_ES_MASK) 353 354 #define TIMERS_TIMER3_CFG_RES_MASK (0x10000U) 355 #define TIMERS_TIMER3_CFG_RES_SHIFT (16U) 356 #define TIMERS_TIMER3_CFG_RES_WIDTH (1U) 357 #define TIMERS_TIMER3_CFG_RES(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER3_CFG_RES_SHIFT)) & TIMERS_TIMER3_CFG_RES_MASK) 358 359 #define TIMERS_TIMER3_CFG_PC_MASK (0x20000U) 360 #define TIMERS_TIMER3_CFG_PC_SHIFT (17U) 361 #define TIMERS_TIMER3_CFG_PC_WIDTH (1U) 362 #define TIMERS_TIMER3_CFG_PC(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER3_CFG_PC_SHIFT)) & TIMERS_TIMER3_CFG_PC_MASK) 363 364 #define TIMERS_TIMER3_CFG_RU_MASK (0x80000U) 365 #define TIMERS_TIMER3_CFG_RU_SHIFT (19U) 366 #define TIMERS_TIMER3_CFG_RU_WIDTH (1U) 367 #define TIMERS_TIMER3_CFG_RU(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER3_CFG_RU_SHIFT)) & TIMERS_TIMER3_CFG_RU_MASK) 368 369 #define TIMERS_TIMER3_CFG_BPEN_MASK (0x100000U) 370 #define TIMERS_TIMER3_CFG_BPEN_SHIFT (20U) 371 #define TIMERS_TIMER3_CFG_BPEN_WIDTH (1U) 372 #define TIMERS_TIMER3_CFG_BPEN(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER3_CFG_BPEN_SHIFT)) & TIMERS_TIMER3_CFG_BPEN_MASK) 373 /*! @} */ 374 375 /*! @name TIMER3_EW - TIMER3 EW */ 376 /*! @{ */ 377 378 #define TIMERS_TIMER3_EW_EW_MASK (0x1U) 379 #define TIMERS_TIMER3_EW_EW_SHIFT (0U) 380 #define TIMERS_TIMER3_EW_EW_WIDTH (1U) 381 #define TIMERS_TIMER3_EW_EW(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER3_EW_EW_SHIFT)) & TIMERS_TIMER3_EW_EW_MASK) 382 /*! @} */ 383 384 /*! @name TIMER3_CC - TIMER3 CC */ 385 /*! @{ */ 386 387 #define TIMERS_TIMER3_CC_CC_MASK (0xFFFFFFFFU) 388 #define TIMERS_TIMER3_CC_CC_SHIFT (0U) 389 #define TIMERS_TIMER3_CC_CC_WIDTH (32U) 390 #define TIMERS_TIMER3_CC_CC(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER3_CC_CC_SHIFT)) & TIMERS_TIMER3_CC_CC_MASK) 391 /*! @} */ 392 393 /*! @name TIMER3_SC - TIMER3 SC */ 394 /*! @{ */ 395 396 #define TIMERS_TIMER3_SC_SC_MASK (0xFFFFFFFFU) 397 #define TIMERS_TIMER3_SC_SC_SHIFT (0U) 398 #define TIMERS_TIMER3_SC_SC_WIDTH (32U) 399 #define TIMERS_TIMER3_SC_SC(x) (((uint32_t)(((uint32_t)(x)) << TIMERS_TIMER3_SC_SC_SHIFT)) & TIMERS_TIMER3_SC_SC_MASK) 400 /*! @} */ 401 402 /*! 403 * @} 404 */ /* end of group TIMERS_Register_Masks */ 405 406 /*! 407 * @} 408 */ /* end of group TIMERS_Peripheral_Access_Layer */ 409 410 #endif /* #if !defined(S32Z2_TIMERS_H_) */ 411
