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Searched refs:TCR (Results 1 – 25 of 324) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/lpflexcomm/lpspi/
Dfsl_lpspi.c252 base->TCR = LPSPI_TCR_CPOL(masterConfig->cpol) | LPSPI_TCR_CPHA(masterConfig->cpha) | in LPSPI_MasterInit()
352 base->TCR = LPSPI_TCR_CPOL(slaveConfig->cpol) | LPSPI_TCR_CPHA(slaveConfig->cpha) | in LPSPI_SlaveInit()
678 …srcClock_Hz / s_baudratePrescaler[(base->TCR & LPSPI_TCR_PRESCALE_MASK) >> LPSPI_TCR_PRESCALE_SHIF…
827 uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1U;
944 …uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + …
968 base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK |
979 …base->TCR |= LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_CONTC(isPcsContinuous) | LPSPI_TCR_RXMSK(…
1030 base->TCR |= LPSPI_TCR_TXMSK_MASK;
1036 … base->TCR &= ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK | LPSPI_TCR_TXMSK_MASK);
1107 base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK));
[all …]
Dfsl_lpspi.h766 base->TCR = (base->TCR & (~LPSPI_TCR_PCS_MASK)) | LPSPI_TCR_PCS((uint8_t)select); in LPSPI_SelectTransferPCS()
784 base->TCR |= LPSPI_TCR_CONT_MASK; in LPSPI_SetPCSContinous()
788 base->TCR &= ~LPSPI_TCR_CONT_MASK; in LPSPI_SetPCSContinous()
871 base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1U); in LPSPI_SetFrameSize()
Dfsl_lpspi_edma.c216 …uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + … in LPSPI_MasterTransferPrepareEDMALite()
237 …base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSP… in LPSPI_MasterTransferPrepareEDMALite()
303 …uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + … in LPSPI_MasterTransferEDMALite()
479 handle->transmitCommand = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK); in LPSPI_MasterTransferEDMALite()
484 transferConfigTx.destAddr = (uint32_t) & (base->TCR); in LPSPI_MasterTransferEDMALite()
802 …uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + … in LPSPI_SlaveTransferEDMA()
834 base->TCR = in LPSPI_SlaveTransferEDMA()
835 …(base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_TXMSK_… in LPSPI_SlaveTransferEDMA()
/hal_nxp-latest/mcux/mcux-sdk/drivers/lpspi/
Dfsl_lpspi.c334 base->TCR = LPSPI_TCR_CPOL(masterConfig->cpol) | LPSPI_TCR_CPHA(masterConfig->cpha) | in LPSPI_MasterInit()
430 base->TCR = LPSPI_TCR_CPOL(slaveConfig->cpol) | LPSPI_TCR_CPHA(slaveConfig->cpha) | in LPSPI_SlaveInit()
748 …srcClock_Hz / s_baudratePrescaler[(base->TCR & LPSPI_TCR_PRESCALE_MASK) >> LPSPI_TCR_PRESCALE_SHIF…
884 uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1U;
952 …uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) …
993 base->TCR |= LPSPI_TCR_TXMSK_MASK;
999 … base->TCR &= ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK | LPSPI_TCR_TXMSK_MASK);
1094 base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK));
1209 …uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + …
1225 base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK |
[all …]
Dfsl_lpspi.h779 base->TCR = (base->TCR & (~LPSPI_TCR_PCS_MASK)) | LPSPI_TCR_PCS((uint8_t)select); in LPSPI_SelectTransferPCS()
797 base->TCR |= LPSPI_TCR_CONT_MASK; in LPSPI_SetPCSContinous()
801 base->TCR &= ~LPSPI_TCR_CONT_MASK; in LPSPI_SetPCSContinous()
842 uint32_t tcr = base->TCR; in LPSPI_FlushFifo()
853 base->TCR = tcr; in LPSPI_FlushFifo()
917 base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1U); in LPSPI_SetFrameSize()
Dfsl_lpspi_edma.c229 …uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + … in LPSPI_MasterTransferPrepareEDMALite()
250 …base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSP… in LPSPI_MasterTransferPrepareEDMALite()
317 …uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + … in LPSPI_MasterTransferEDMALite()
532 handle->transmitCommand = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK); in LPSPI_MasterTransferEDMALite()
536 transferConfigTx.destAddr = (uint32_t) & (base->TCR); in LPSPI_MasterTransferEDMALite()
948 …uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + … in LPSPI_SlaveTransferEDMA()
980 base->TCR = in LPSPI_SlaveTransferEDMA()
981 …(base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_TXMSK_… in LPSPI_SlaveTransferEDMA()
/hal_nxp-latest/mcux/mcux-sdk/drivers/esai/
Dfsl_esai.c163 … base->TCR &= ~(ESAI_TCR_PADC_MASK | ESAI_TCR_TFSR_MASK | ESAI_TCR_TFSL_MASK | ESAI_TCR_TWA_MASK | in ESAI_SetCustomerProtocol()
166 base->TCR |= ESAI_TCR_PADC(protocol->ifZeroPading) | ESAI_TCR_TFSR(protocol->fsEarly) | in ESAI_SetCustomerProtocol()
528 …base->TCR &= ~(ESAI_TCR_TE0_MASK | ESAI_TCR_TE1_MASK | ESAI_TCR_TE2_MASK | ESAI_TCR_TE3_MASK | ESA… in ESAI_TxReset()
530 base->TCR |= ESAI_TCR_TPR_MASK; in ESAI_TxReset()
533 base->TCR &= ~ESAI_TCR_TPR_MASK; in ESAI_TxReset()
588 …val = base->TCR & ~(ESAI_TCR_TE5_MASK | ESAI_TCR_TE4_MASK | ESAI_TCR_TE3_MASK | ESAI_TCR_TE2_MASK | in ESAI_TxEnable()
591 base->TCR = val; in ESAI_TxEnable()
647 base->TCR &= ~ESAI_TCR_TSWS_MASK; in ESAI_TxSetFormat()
648 base->TCR |= ESAI_TCR_TSWS(format->slotType); in ESAI_TxSetFormat()
1239 ((ESAI->TCR & (uint32_t)kESAI_TransmitInterruptEnable) != 0U)) in ESAI_DriverIRQHandler()
[all …]
Dfsl_esai.h556 base->TCR |= mask; in ESAI_TxEnableInterrupts()
578 base->TCR &= (~mask); in ESAI_TxDisableInterrupts()
/hal_nxp-latest/mcux/mcux-sdk/drivers/ctimer/
Dfsl_ctimer.h499 base->TCR |= CTIMER_TCR_CEN_MASK; in CTIMER_StartTimer()
509 base->TCR &= ~CTIMER_TCR_CEN_MASK; in CTIMER_StopTimer()
523 base->TCR |= CTIMER_TCR_CRST_MASK; in CTIMER_Reset()
524 base->TCR &= ~CTIMER_TCR_CRST_MASK; in CTIMER_Reset()
/hal_nxp-latest/mcux/mcux-sdk/components/serial_manager/
Dfsl_component_serial_port_swo.c86 ITM->TCR = 0U; in Serial_SwoInit()
94 ITM->TCR = ITM_TCR_ITMENA_Msk | ITM_TCR_SYNCENA_Msk in Serial_SwoInit()
135 assert((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0U); in Serial_SwoWrite()
/hal_nxp-latest/mcux/mcux-sdk/drivers/smartcard/
Dfsl_smartcard_usim.c371 CTIMER0->TCR &= ~CTIMER_TCR_CEN_MASK; in SMARTCARD_USIM_TimerInit()
402 CTIMER0->TCR |= CTIMER_TCR_CEN_MASK; in SMARTCARD_USIM_TimerStart()
411 CTIMER0->TCR &= ~CTIMER_TCR_CEN_MASK; in SMARTCARD_USIM_TimerStop()
/hal_nxp-latest/mcux/mcux-sdk/drivers/mu1/
Dfsl_mu.h655 base->TCR |= tmp; in MU_EnableInterrupts()
711 base->TCR &= ~tmp; in MU_DisableInterrupts()
/hal_nxp-latest/mcux/mcux-sdk/cmsis_drivers/enet/
Dfsl_enet_cmsis.c160 uint32_t tcr = enet->resource->base->TCR; in ENET_CommonControl()
253 enet->resource->base->TCR = tcr; in ENET_CommonControl()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/
Dfsl_sentinel.c26 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0x120 */ member
74 SENTINEL__MUA_RTD->TCR = 0U; /* Disable all transmit interrupts. */ in SENTINEL_Init()
/hal_nxp-latest/mcux/mcux-sdk/cmsis_drivers/lpspi/
Dfsl_lpspi_cmsis.c611 …uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_T… in LPSPI_EdmaSend()
652 …uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_T… in LPSPI_EdmaReceive()
696 …uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_T… in LPSPI_EdmaTransfer()
735 …uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_… in LPSPI_EdmaGetCount()
1022 …uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_T… in LPSPI_InterruptSend()
1063 …uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_T… in LPSPI_InterruptReceive()
1107 …uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_T… in LPSPI_InterruptTransfer()
1146 …uint32_t datawidth = (lpspi->resource->base->TCR & (uint32_t)LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_… in LPSPI_InterruptGetCount()
/hal_nxp-latest/mcux/mcux-sdk/drivers/dac14/
Dfsl_dac14.h408 base->TCR = HPDAC_TCR_SWTRG_MASK; in DAC14_DoSoftwareTrigger()
/hal_nxp-latest/mcux/middleware/mcux-sdk-middleware-multicore/mcmgr/src/
Dmcmgr_mu_internal.c93 if ((0UL != (flags & (1UL << i))) && (0UL != (base->TCR & (1UL << tcr_tie_idx)))) in mu_isr()
/hal_nxp-latest/mcux/mcux-sdk/drivers/dac_1/
Dfsl_dac.h430 base->TCR = LPDAC_TCR_SWTRG_MASK; in DAC_DoSoftwareTriggerFIFO()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/drivers/upower/
Dupower_api.c252 mu->TCR.R = 0U; /* disable the tx interrupts */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
3122 mu->TCR.R = 1UL << (size - 1UL); in upwr_tx()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/drivers/upower/
Dupower_api.c252 mu->TCR.R = 0U; /* disable the tx interrupts */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
3122 mu->TCR.R = 1UL << (size - 1UL); in upwr_tx()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/drivers/upower/
Dupower_api.c252 mu->TCR.R = 0U; /* disable the tx interrupts */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
3122 mu->TCR.R = 1UL << (size - 1UL); in upwr_tx()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/drivers/upower/
Dupower_api.c252 mu->TCR.R = 0U; /* disable the tx interrupts */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
3122 mu->TCR.R = 1UL << (size - 1UL); in upwr_tx()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/drivers/upower/
Dupower_api.c252 mu->TCR.R = 0U; /* disable the tx interrupts */ in upwr_txrx_isr()
579 mu->TCR.R = mu->RCR.R = 0U; /* disable tx and rx interrupts, in case in upwr_init()
3122 mu->TCR.R = 1UL << (size - 1UL); in upwr_tx()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_RTC.h76 …__IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC … member
DS32K142W_RTC.h76 …__IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC … member

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