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Searched refs:TCD (Results 1 – 25 of 103) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/
Dsystem_MIMXRT1189_cm33.c188 DMA4->TCD[0].SADDR = 0x20484000; in InitCM7DMA()
189 DMA4->TCD[0].DADDR = targetAddr; in InitCM7DMA()
190 DMA4->TCD[0].NBYTES_MLOFFNO = 0x20000; in InitCM7DMA()
191 DMA4->TCD[0].CITER_ELINKNO = 0x1; in InitCM7DMA()
192 DMA4->TCD[0].BITER_ELINKNO = 0x1; in InitCM7DMA()
193 DMA4->TCD[0].ATTR = 0x303; in InitCM7DMA()
194 DMA4->TCD[0].SOFF = 0; in InitCM7DMA()
195 DMA4->TCD[0].DOFF = 0x8; in InitCM7DMA()
196 DMA4->TCD[0].CH_CSR = 0x7; in InitCM7DMA()
197 DMA4->TCD[0].CSR = 0x8; in InitCM7DMA()
[all …]
Dsystem_MIMXRT1189_cm7.c161 DMA4->TCD[0].CH_ES = DMA_CH_ES_ERR_MASK; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/
Dsystem_MIMXRT1187_cm33.c199 DMA4->TCD[0].SADDR = 0x20484000; in InitCM7DMA()
200 DMA4->TCD[0].DADDR = targetAddr; in InitCM7DMA()
201 DMA4->TCD[0].NBYTES_MLOFFNO = 0x20000; in InitCM7DMA()
202 DMA4->TCD[0].CITER_ELINKNO = 0x1; in InitCM7DMA()
203 DMA4->TCD[0].BITER_ELINKNO = 0x1; in InitCM7DMA()
204 DMA4->TCD[0].ATTR = 0x303; in InitCM7DMA()
205 DMA4->TCD[0].SOFF = 0; in InitCM7DMA()
206 DMA4->TCD[0].DOFF = 0x8; in InitCM7DMA()
207 DMA4->TCD[0].CH_CSR = 0x7; in InitCM7DMA()
208 DMA4->TCD[0].CSR = 0x8; in InitCM7DMA()
[all …]
Dsystem_MIMXRT1187_cm7.c164 DMA4->TCD[0].CH_ES = DMA_CH_ES_ERR_MASK; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/drivers/edma/
Dfsl_edma.c95 base->TCD[channel].SADDR = tcd->SADDR; in EDMA_InstallTCD()
96 base->TCD[channel].SOFF = tcd->SOFF; in EDMA_InstallTCD()
97 base->TCD[channel].ATTR = tcd->ATTR; in EDMA_InstallTCD()
98 base->TCD[channel].NBYTES_MLNO = tcd->NBYTES; in EDMA_InstallTCD()
99 base->TCD[channel].SLAST = (int32_t)tcd->SLAST; in EDMA_InstallTCD()
100 base->TCD[channel].DADDR = tcd->DADDR; in EDMA_InstallTCD()
101 base->TCD[channel].DOFF = tcd->DOFF; in EDMA_InstallTCD()
102 base->TCD[channel].CITER_ELINKNO = tcd->CITER; in EDMA_InstallTCD()
103 base->TCD[channel].DLAST_SGA = (int32_t)tcd->DLAST_SGA; in EDMA_InstallTCD()
105 base->TCD[channel].CSR = 0; in EDMA_InstallTCD()
[all …]
Dfsl_edma.h510 base->TCD[channel].CSR = in EDMA_EnableAutoStopRequest()
511 …(uint16_t)((base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0… in EDMA_EnableAutoStopRequest()
977 return (uint32_t)(handle->base->TCD[handle->channel].DLAST_SGA); in EDMA_GetNextTCDAddress()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1180/jlinkscript/
Devkmimxrt1180_cm33.jlinkscript390 _WriteViaCM33AP32(0x5201002C, 0x00000000); // DMA4->TCD[0].SLAST_SGA
391 _WriteViaCM33AP32(0x52010038, 0x00000000); // DMA4->TCD[0].DLAST_SGA
393 _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TCD[0].CH_CSR
395 _WriteViaCM33AP32(0x52010020, 0x20484000); // DMA4->TCD[0].SADDR
396 _WriteViaCM33AP32(0x52010030, targetAddr); // DMA4->TCD[0].DADDR
397 _WriteViaCM33AP32(0x52010028, size); // DMA4->TCD[0].NBYTES_MLOFFNO
398 _WriteViaCM33AP16(0x52010036, 0x1); // DMA4->TCD[0].ELINKNO
399 _WriteViaCM33AP16(0x5201003E, 0x1); // DMA4->TCD[0].BITER_ELINKNO
400 _WriteViaCM33AP16(0x52010026, 0x0303); // DMA4->TCD[0].ATTR
401 _WriteViaCM33AP16(0x52010024, 0x0); // DMA4->TCD[0].SOFF
[all …]
Devkmimxrt1180_cm7.jlinkscript390 _WriteViaCM33AP32(0x5201002C, 0x00000000); // DMA4->TCD[0].SLAST_SGA
391 _WriteViaCM33AP32(0x52010038, 0x00000000); // DMA4->TCD[0].DLAST_SGA
393 _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TCD[0].CH_CSR
395 _WriteViaCM33AP32(0x52010020, 0x20484000); // DMA4->TCD[0].SADDR
396 _WriteViaCM33AP32(0x52010030, targetAddr); // DMA4->TCD[0].DADDR
397 _WriteViaCM33AP32(0x52010028, size); // DMA4->TCD[0].NBYTES_MLOFFNO
398 _WriteViaCM33AP16(0x52010036, 0x1); // DMA4->TCD[0].ELINKNO
399 _WriteViaCM33AP16(0x5201003E, 0x1); // DMA4->TCD[0].BITER_ELINKNO
400 _WriteViaCM33AP16(0x52010026, 0x0303); // DMA4->TCD[0].ATTR
401 _WriteViaCM33AP16(0x52010024, 0x0); // DMA4->TCD[0].SOFF
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/qspi/
Dfsl_qspi_edma.c286 handle->dmaHandle->base->TCD[handle->dmaHandle->channel].ATTR |= DMA_ATTR_SMOD(0x5U); in QSPI_TransferReceiveEDMA()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_EDMA3_TCD.h104 } TCD[EDMA3_TCD_TCD_COUNT]; member
DS32Z2_FEED_DMA_TCD.h104 } TCD[FEED_DMA_TCD_TCD_COUNT]; member
DS32Z2_RESULT_DMA_TCD.h104 } TCD[RESULT_DMA_TCD_TCD_COUNT]; member
DS32Z2_EDMA4_TCD.h106 } TCD[EDMA4_TCD_TCD_COUNT]; member
/hal_nxp-latest/mcux/
DREADME123 - drivers: edma_rev2: support 64-bit TCD registers
/hal_nxp-latest/mcux/mcux-sdk/drivers/spdif/
Dfsl_spdif_edma.c134 edma_tcd_t *tcdRegs = (edma_tcd_t *)(uint32_t)&handle->base->TCD[handle->channel]; in SPDIF_SubmitTransfer()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K118_DMA.h124 } TCD[DMA_TCD_COUNT]; member
DS32K116_DMA.h124 } TCD[DMA_TCD_COUNT]; member
DS32K148_DMA.h124 } TCD[DMA_TCD_COUNT]; member
DS32K144W_DMA.h124 } TCD[DMA_TCD_COUNT]; member
DS32K144_DMA.h124 } TCD[DMA_TCD_COUNT]; member
DS32K142W_DMA.h124 } TCD[DMA_TCD_COUNT]; member
DS32K142_DMA.h124 } TCD[DMA_TCD_COUNT]; member
DS32K146_DMA.h124 } TCD[DMA_TCD_COUNT]; member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h1597 } TCD[4]; member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h1601 } TCD[4]; member

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