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Searched refs:TBSR (Results 1 – 25 of 48) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h98 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ member
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h104 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ member
/hal_nxp-latest/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h748 uint32 RegValue = (uint32)BaseAddr->TBSR; in Qspi_Ip_GetTxBufFill()
/hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/include/
DQspi_Ip_HwAccess.h1068 uint32 RegValue = (uint32)BaseAddr->TBSR; in Qspi_Ip_GetTxBufFill()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_NETC_F3_SI5.h212 …__IO uint32_t TBSR; /**< Tx BDR 0 status register..Tx BDR 17 status r… member
DS32Z2_NETC_F3_SI6.h212 …__IO uint32_t TBSR; /**< Tx BDR 0 status register..Tx BDR 17 status r… member
DS32Z2_NETC_F3_SI7.h212 …__IO uint32_t TBSR; /**< Tx BDR 0 status register..Tx BDR 17 status r… member
DS32Z2_NETC_F3_SI4.h212 …__IO uint32_t TBSR; /**< Tx BDR 0 status register..Tx BDR 17 status r… member
DS32Z2_QUADSPI.h114 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ member
DS32Z2_NETC_F3_SI1.h212 …__IO uint32_t TBSR; /**< Tx BDR 0 status register..Tx BDR 17 status r… member
DS32Z2_NETC_F3_SI2.h212 …__IO uint32_t TBSR; /**< Tx BDR 0 status register..Tx BDR 17 status r… member
DS32Z2_NETC_F3_SI3.h212 …__IO uint32_t TBSR; /**< Tx BDR 0 status register..Tx BDR 17 status r… member
DS32Z2_NETC_F3_SI0.h214 …__IO uint32_t TBSR; /**< Tx BDR 0 status register..Tx BDR 17 status r… member
/hal_nxp-latest/s32/drivers/s32ze/Eth_NETC/src/
DNetc_Eth_Ip.c5480 sbStatus= netcSIsBase[siIndex]->BDR_NUM[idx].TBSR;
5485 netcSIsBase[siIndex]->BDR_NUM[idx].TBSR = sbStatus;
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18276 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19249 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ member
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h30434 …__I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x1… member
30481 #define QuadSPI_TBSR_REG(base) ((base)->TBSR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h17780 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h17778 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ member
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h37632 …__I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x1… member
37679 #define QuadSPI_TBSR_REG(base) ((base)->TBSR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h27225 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h27226 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h63492 __I uint32_t TBSR; /**< TX Buffer Status, offset: 0x150 */ member
DMIMXRT735S_cm33_core1.h63561 __I uint32_t TBSR; /**< TX Buffer Status, offset: 0x150 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h44008 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ member

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