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Searched refs:TBDR (Results 1 – 25 of 36) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/qspi/
Dfsl_qspi.h503 return (uint32_t)(&base->TBDR); in QSPI_GetTxDataRegisterAddress()
683 base->TBDR = data; in QSPI_WriteData()
Dfsl_qspi.c520 base->TBDR = *buffer++; in QSPI_WriteBlocking()
/hal_nxp-latest/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h775 BaseAddr->TBDR = Data; in Qspi_Ip_WriteTxData()
784 return (Qspi_Ip_UintPtrType)&(BaseAddr->TBDR); in Qspi_Ip_GetTxDataAddr()
/hal_nxp-latest/mcux/mcux-sdk/drivers/xspi/
Dfsl_xspi.h1244 return (uint32_t)&base->TBDR; in XSPI_GetTxFifoAddress()
1389 base->TBDR = data; in XSPI_WriteTxBuffer()
Dfsl_xspi.c1365 base->TBDR = *(uint32_t *)buffer; in XSPI_WriteBlocking()
1385 base->TBDR = tempVal; in XSPI_WriteBlocking()
/hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/include/
DQspi_Ip_HwAccess.h1096 BaseAddr->TBDR = Data; in Qspi_Ip_WriteTxData()
1105 return (Qspi_Ip_UintPtrType)&(BaseAddr->TBDR); in Qspi_Ip_GetTxDataAddr()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h99 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ member
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h105 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ member
/hal_nxp-latest/s32/drivers/s32k3/Fls/src/
DQspi_Ip_Controller.c2041 BaseAddr->TBDR = (uint32)0x00000000UL; in Qspi_Ip_ResetAllRegisters()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h115 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18277 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19250 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ member
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h30435 …__IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154… member
30482 #define QuadSPI_TBDR_REG(base) ((base)->TBDR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h17781 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h17779 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ member
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h37633 …__IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154… member
37680 #define QuadSPI_TBDR_REG(base) ((base)->TBDR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h27226 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h27227 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h63493 __IO uint32_t TBDR; /**< TX Buffer Data, offset: 0x154 */ member
DMIMXRT735S_cm33_core1.h63562 __IO uint32_t TBDR; /**< TX Buffer Data, offset: 0x154 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h44009 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h66785 __IO uint32_t TBDR; /**< TX Buffer Data, offset: 0x154 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h46182 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h46182 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h66714 __IO uint32_t TBDR; /**< TX Buffer Data, offset: 0x154 */ member

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