1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_GPR4.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_GPR4 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_GPR4_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_GPR4_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- GPR4 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup GPR4_Peripheral_Access_Layer GPR4 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** GPR4 - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t LVFCCUGD4; /**< VFCCU Global DID register 4, offset: 0x0 */ 74 __IO uint32_t LVFCCULD12; /**< VFCCU Local DID register 12, offset: 0x4 */ 75 __IO uint32_t LVFCCULD13; /**< VFCCU Local DID register 13, offset: 0x8 */ 76 __IO uint32_t LVFCCULD14; /**< VFCCU Local DID register 14, offset: 0xC */ 77 uint8_t RESERVED_0[52]; 78 __I uint32_t INITM4; /**< NoC Initiator NIU Timeout Status, offset: 0x44 */ 79 __I uint32_t TARGTMS4; /**< NoC Target NIU Timeout Status, offset: 0x48 */ 80 __IO uint32_t TARGTMC4; /**< NoC Target NIU Timeout Control, offset: 0x4C */ 81 uint8_t RESERVED_1[4]; 82 __IO uint32_t CLKOUT2SEL; /**< CLKOUT_2 MUX select, offset: 0x54 */ 83 uint8_t RESERVED_2[56]; 84 __IO uint32_t MEW0MSTDIS; /**< MEW_0 Master ID Disable, offset: 0x90 */ 85 __IO uint32_t MEW1MSTDIS; /**< MEW_1 Master ID Disable, offset: 0x94 */ 86 uint8_t RESERVED_3[8]; 87 __IO uint32_t HSE_SYS_FUSEC; /**< System Fuse Update Disable, offset: 0xA0 */ 88 } GPR4_Type, *GPR4_MemMapPtr; 89 90 /** Number of instances of the GPR4 module. */ 91 #define GPR4_INSTANCE_COUNT (1u) 92 93 /* GPR4 - Peripheral instance base addresses */ 94 /** Peripheral GPR4 base address */ 95 #define IP_GPR4_BASE (0x42060000u) 96 /** Peripheral GPR4 base pointer */ 97 #define IP_GPR4 ((GPR4_Type *)IP_GPR4_BASE) 98 /** Array initializer of GPR4 peripheral base addresses */ 99 #define IP_GPR4_BASE_ADDRS { IP_GPR4_BASE } 100 /** Array initializer of GPR4 peripheral base pointers */ 101 #define IP_GPR4_BASE_PTRS { IP_GPR4 } 102 103 /* ---------------------------------------------------------------------------- 104 -- GPR4 Register Masks 105 ---------------------------------------------------------------------------- */ 106 107 /*! 108 * @addtogroup GPR4_Register_Masks GPR4 Register Masks 109 * @{ 110 */ 111 112 /*! @name LVFCCUGD4 - VFCCU Global DID register 4 */ 113 /*! @{ */ 114 115 #define GPR4_LVFCCUGD4_FHID_MASK (0xFU) 116 #define GPR4_LVFCCUGD4_FHID_SHIFT (0U) 117 #define GPR4_LVFCCUGD4_FHID_WIDTH (4U) 118 #define GPR4_LVFCCUGD4_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR4_LVFCCUGD4_FHID_SHIFT)) & GPR4_LVFCCUGD4_FHID_MASK) 119 /*! @} */ 120 121 /*! @name LVFCCULD12 - VFCCU Local DID register 12 */ 122 /*! @{ */ 123 124 #define GPR4_LVFCCULD12_FHID_MASK (0xFFFFFFFFU) 125 #define GPR4_LVFCCULD12_FHID_SHIFT (0U) 126 #define GPR4_LVFCCULD12_FHID_WIDTH (32U) 127 #define GPR4_LVFCCULD12_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR4_LVFCCULD12_FHID_SHIFT)) & GPR4_LVFCCULD12_FHID_MASK) 128 /*! @} */ 129 130 /*! @name LVFCCULD13 - VFCCU Local DID register 13 */ 131 /*! @{ */ 132 133 #define GPR4_LVFCCULD13_FHID_MASK (0xFFFFFFFFU) 134 #define GPR4_LVFCCULD13_FHID_SHIFT (0U) 135 #define GPR4_LVFCCULD13_FHID_WIDTH (32U) 136 #define GPR4_LVFCCULD13_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR4_LVFCCULD13_FHID_SHIFT)) & GPR4_LVFCCULD13_FHID_MASK) 137 /*! @} */ 138 139 /*! @name LVFCCULD14 - VFCCU Local DID register 14 */ 140 /*! @{ */ 141 142 #define GPR4_LVFCCULD14_FHID_MASK (0xFFFFFFFFU) 143 #define GPR4_LVFCCULD14_FHID_SHIFT (0U) 144 #define GPR4_LVFCCULD14_FHID_WIDTH (32U) 145 #define GPR4_LVFCCULD14_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR4_LVFCCULD14_FHID_SHIFT)) & GPR4_LVFCCULD14_FHID_MASK) 146 /*! @} */ 147 148 /*! @name INITM4 - NoC Initiator NIU Timeout Status */ 149 /*! @{ */ 150 151 #define GPR4_INITM4_STAT_MASK (0xFFFFFFFFU) 152 #define GPR4_INITM4_STAT_SHIFT (0U) 153 #define GPR4_INITM4_STAT_WIDTH (32U) 154 #define GPR4_INITM4_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR4_INITM4_STAT_SHIFT)) & GPR4_INITM4_STAT_MASK) 155 /*! @} */ 156 157 /*! @name TARGTMS4 - NoC Target NIU Timeout Status */ 158 /*! @{ */ 159 160 #define GPR4_TARGTMS4_STAT_MASK (0xFFFFFFFFU) 161 #define GPR4_TARGTMS4_STAT_SHIFT (0U) 162 #define GPR4_TARGTMS4_STAT_WIDTH (32U) 163 #define GPR4_TARGTMS4_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR4_TARGTMS4_STAT_SHIFT)) & GPR4_TARGTMS4_STAT_MASK) 164 /*! @} */ 165 166 /*! @name TARGTMC4 - NoC Target NIU Timeout Control */ 167 /*! @{ */ 168 169 #define GPR4_TARGTMC4_EN_MASK (0xFFFFFFFFU) 170 #define GPR4_TARGTMC4_EN_SHIFT (0U) 171 #define GPR4_TARGTMC4_EN_WIDTH (32U) 172 #define GPR4_TARGTMC4_EN(x) (((uint32_t)(((uint32_t)(x)) << GPR4_TARGTMC4_EN_SHIFT)) & GPR4_TARGTMC4_EN_MASK) 173 /*! @} */ 174 175 /*! @name CLKOUT2SEL - CLKOUT_2 MUX select */ 176 /*! @{ */ 177 178 #define GPR4_CLKOUT2SEL_MUXSEL_MASK (0x1FU) 179 #define GPR4_CLKOUT2SEL_MUXSEL_SHIFT (0U) 180 #define GPR4_CLKOUT2SEL_MUXSEL_WIDTH (5U) 181 #define GPR4_CLKOUT2SEL_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << GPR4_CLKOUT2SEL_MUXSEL_SHIFT)) & GPR4_CLKOUT2SEL_MUXSEL_MASK) 182 /*! @} */ 183 184 /*! @name MEW0MSTDIS - MEW_0 Master ID Disable */ 185 /*! @{ */ 186 187 #define GPR4_MEW0MSTDIS_MSTRDIS_MASK (0x1U) 188 #define GPR4_MEW0MSTDIS_MSTRDIS_SHIFT (0U) 189 #define GPR4_MEW0MSTDIS_MSTRDIS_WIDTH (1U) 190 #define GPR4_MEW0MSTDIS_MSTRDIS(x) (((uint32_t)(((uint32_t)(x)) << GPR4_MEW0MSTDIS_MSTRDIS_SHIFT)) & GPR4_MEW0MSTDIS_MSTRDIS_MASK) 191 192 #define GPR4_MEW0MSTDIS_MID_MASK (0x7EU) 193 #define GPR4_MEW0MSTDIS_MID_SHIFT (1U) 194 #define GPR4_MEW0MSTDIS_MID_WIDTH (6U) 195 #define GPR4_MEW0MSTDIS_MID(x) (((uint32_t)(((uint32_t)(x)) << GPR4_MEW0MSTDIS_MID_SHIFT)) & GPR4_MEW0MSTDIS_MID_MASK) 196 /*! @} */ 197 198 /*! @name MEW1MSTDIS - MEW_1 Master ID Disable */ 199 /*! @{ */ 200 201 #define GPR4_MEW1MSTDIS_MSTRDIS_MASK (0x1U) 202 #define GPR4_MEW1MSTDIS_MSTRDIS_SHIFT (0U) 203 #define GPR4_MEW1MSTDIS_MSTRDIS_WIDTH (1U) 204 #define GPR4_MEW1MSTDIS_MSTRDIS(x) (((uint32_t)(((uint32_t)(x)) << GPR4_MEW1MSTDIS_MSTRDIS_SHIFT)) & GPR4_MEW1MSTDIS_MSTRDIS_MASK) 205 206 #define GPR4_MEW1MSTDIS_MID_MASK (0x7EU) 207 #define GPR4_MEW1MSTDIS_MID_SHIFT (1U) 208 #define GPR4_MEW1MSTDIS_MID_WIDTH (6U) 209 #define GPR4_MEW1MSTDIS_MID(x) (((uint32_t)(((uint32_t)(x)) << GPR4_MEW1MSTDIS_MID_SHIFT)) & GPR4_MEW1MSTDIS_MID_MASK) 210 /*! @} */ 211 212 /*! @name HSE_SYS_FUSEC - System Fuse Update Disable */ 213 /*! @{ */ 214 215 #define GPR4_HSE_SYS_FUSEC_CTRL_MASK (0x1U) 216 #define GPR4_HSE_SYS_FUSEC_CTRL_SHIFT (0U) 217 #define GPR4_HSE_SYS_FUSEC_CTRL_WIDTH (1U) 218 #define GPR4_HSE_SYS_FUSEC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GPR4_HSE_SYS_FUSEC_CTRL_SHIFT)) & GPR4_HSE_SYS_FUSEC_CTRL_MASK) 219 /*! @} */ 220 221 /*! 222 * @} 223 */ /* end of group GPR4_Register_Masks */ 224 225 /*! 226 * @} 227 */ /* end of group GPR4_Peripheral_Access_Layer */ 228 229 #endif /* #if !defined(S32Z2_GPR4_H_) */ 230
