| /hal_nxp-latest/s32/drivers/s32k3/Fls/include/ |
| D | Qspi_Ip_Controller.h | 103 #define Qspi_Ip_WriteLuts(Instance, StartLutRegister, Data, Size) \ argument
104 … OsIf_Trusted_Call4params(Qspi_Ip_WriteLuts_Privileged, Instance, StartLutRegister, Data, Size)
110 #define Qspi_Ip_WriteLuts(Instance, StartLutRegister, Data, Size) \
111 Qspi_Ip_WriteLuts_Privileged(Instance, StartLutRegister, Data, Size)
190 uint8 Size
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| D | Qspi_Ip_HwAccess.h | 555 uint16 Size, in Qspi_Ip_SetAhbBuf0() argument
559 BaseAddr->BUF0CR = QuadSPI_BUF0CR_ADATSZ((uint32)Size >> 3U) in Qspi_Ip_SetAhbBuf0()
568 uint16 Size, in Qspi_Ip_SetAhbBuf1() argument
572 BaseAddr->BUF1CR = QuadSPI_BUF1CR_ADATSZ((uint32)Size >> 3U) in Qspi_Ip_SetAhbBuf1()
581 uint16 Size, in Qspi_Ip_SetAhbBuf2() argument
585 BaseAddr->BUF2CR = QuadSPI_BUF2CR_ADATSZ((uint32)Size >> 3U) in Qspi_Ip_SetAhbBuf2()
594 uint16 Size, in Qspi_Ip_SetAhbBuf3() argument
599 BaseAddr->BUF3CR = QuadSPI_BUF3CR_ADATSZ((uint32)Size >> 3U) in Qspi_Ip_SetAhbBuf3()
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| D | Qspi_Ip_TrustedFunctions.h | 87 uint8 Size
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| /hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/include/ |
| D | Qspi_Ip_Controller.h | 102 #define Qspi_Ip_WriteLuts(Instance, StartLutRegister, Data, Size) \ argument
103 … OsIf_Trusted_Call4params(Qspi_Ip_WriteLuts_Privileged, Instance, StartLutRegister, Data, Size)
109 #define Qspi_Ip_WriteLuts(Instance, StartLutRegister, Data, Size) \
110 Qspi_Ip_WriteLuts_Privileged(Instance, StartLutRegister, Data, Size)
189 uint8 Size
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| D | Qspi_Ip_HwAccess.h | 852 uint16 Size, in Qspi_Ip_SetAhbBuf0() argument
856 BaseAddr->BUF0CR = QuadSPI_BUF0CR_ADATSZ((uint32)Size >> 3U) in Qspi_Ip_SetAhbBuf0()
865 uint16 Size, in Qspi_Ip_SetAhbBuf1() argument
869 BaseAddr->BUF1CR = QuadSPI_BUF1CR_ADATSZ((uint32)Size >> 3U) in Qspi_Ip_SetAhbBuf1()
878 uint16 Size, in Qspi_Ip_SetAhbBuf2() argument
882 BaseAddr->BUF2CR = QuadSPI_BUF2CR_ADATSZ((uint32)Size >> 3U) in Qspi_Ip_SetAhbBuf2()
891 uint16 Size, in Qspi_Ip_SetAhbBuf3() argument
896 BaseAddr->BUF3CR = QuadSPI_BUF3CR_ADATSZ((uint32)Size >> 3U) in Qspi_Ip_SetAhbBuf3()
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| D | Qspi_Ip_TrustedFunctions.h | 87 uint8 Size
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| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core/Include/ |
| D | mpu_armv7.h | 103 #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) … argument
108 … (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
123 …, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ argument
124 …ion, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
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| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/Include/ |
| D | mpu_armv7.h | 103 #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) … argument
108 … (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
123 …, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ argument
124 …ion, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
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| /hal_nxp-latest/mcux/middleware/mcux-sdk-middleware-connectivity-framework/platform/Common/ |
| D | fwk_platform_mcuboot_ota.ch | 25 * FW_UPDATE_STORAGE_SIZE: Size of the whole firmware update storage section.
82 uint16_t ih_hdr_size; /* Size of image header (bytes). */
83 uint16_t ih_protect_tlv_size; /* Size of protected TLV area (bytes). */
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| /hal_nxp-latest/s32/drivers/s32k3/Fls/src/ |
| D | Qspi_Ip_Controller.c | 1221 uint8 Size in Qspi_Ip_WriteLuts_Privileged() argument
1226 DEV_ASSERT_QSPI(Size <= FEATURE_QSPI_LUT_SEQUENCE_SIZE); in Qspi_Ip_WriteLuts_Privileged()
1227 DEV_ASSERT_QSPI((StartLutRegister + Size) <= QuadSPI_LUT_COUNT); in Qspi_Ip_WriteLuts_Privileged()
1232 for (Idx = 0U; Idx < Size; Idx++) in Qspi_Ip_WriteLuts_Privileged()
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| /hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/src/ |
| D | Qspi_Ip_Controller.c | 1456 uint8 Size in Qspi_Ip_WriteLuts_Privileged() argument
1462 DEV_ASSERT_QSPI(Size <= FEATURE_QSPI_LUT_SEQUENCE_SIZE); in Qspi_Ip_WriteLuts_Privileged()
1463 DEV_ASSERT_QSPI((StartLutRegister + Size) <= QuadSPI_LUT_COUNT); in Qspi_Ip_WriteLuts_Privileged()
1469 for (Idx = 0U; Idx < Size; Idx++) in Qspi_Ip_WriteLuts_Privileged()
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| /hal_nxp-latest/mcux/middleware/wifi_nxp/wifidriver/incl/ |
| D | mlan_ieee.h | 913 t_u16 Size : 15; // ! Nominal size in octets
915 t_u16 Size : 15; // ! Nominal size in octets
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| /hal_nxp-latest/s32/drivers/s32k3/Eth_GMAC/src/ |
| D | Gmac_Ip.c | 268 static uint32 Gmac_Ip_ComputeCRC32(const uint8 *Mac, uint8 Size);
333 static uint32 Gmac_Ip_ComputeCRC32(const uint8 *Mac, uint8 Size) in Gmac_Ip_ComputeCRC32() argument
338 for (i = 0; i < Size; i++) in Gmac_Ip_ComputeCRC32()
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| /hal_nxp-latest/mcux/middleware/mcux-sdk-middleware-multicore/rpmsg_lite/ |
| D | README.md | 116 |RL_BUFFER_PAYLOAD_SIZE | (496) | Size of the buffer payload, it must be equal to (2…
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| /hal_nxp-latest/s32/drivers/s32ze/Eth_NETC/src/ |
| D | Netc_Eth_Ip.c | 1749 …ne void Netc_Eth_Ip_ClearVsiToPsiMsgBuff(Netc_Eth_Ip_VsiToPsiMsgType *MsgCommandConfig, uint8 Size) in Netc_Eth_Ip_ClearVsiToPsiMsgBuff() argument
1756 for(DataIdx = 0; DataIdx < (Size - (uint8) 2U); DataIdx++) in Netc_Eth_Ip_ClearVsiToPsiMsgBuff()
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