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Searched refs:SYS_PLL2_CTRL (Results 1 – 25 of 45) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_clock.c249 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
257 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
259 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
262 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
264 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
276 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
282 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
295 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
301 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
306 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h1645 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1676 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_clock.c249 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
257 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
259 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
262 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
264 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
276 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
282 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
295 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
301 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
306 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h1645 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1676 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_clock.c249 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
257 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
259 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
262 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
264 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
276 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
282 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
295 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
301 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
306 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h1645 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1676 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_clock.c249 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
257 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
259 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
262 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
264 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
276 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
282 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
295 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
301 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
306 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h1645 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1676 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_clock.c285 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
293 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
295 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
298 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
300 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
312 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
318 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
332 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
339 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
344 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h2202 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2233 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_clock.c285 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
293 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
295 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
298 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
300 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
312 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
318 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
332 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
339 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
344 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h2202 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2233 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_clock.c285 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
293 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
295 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
298 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
300 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
312 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
318 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
331 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
337 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
342 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h2169 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2200 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_clock.c285 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
293 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
295 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
298 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
300 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
312 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
318 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
332 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
339 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
344 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h2202 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2233 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_clock.c285 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
293 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
295 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
298 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
300 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
312 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
318 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
332 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
339 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
344 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h2202 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2233 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_clock.c285 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
293 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
295 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
298 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
300 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
312 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
318 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
332 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
339 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
344 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_clock.c285 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
293 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
295 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
298 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
300 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
312 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
318 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
331 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
337 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
342 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1175/
Dfsl_pm_device.c891 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
939 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1171/
Dfsl_pm_device.c891 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
939 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1172/
Dfsl_pm_device.c891 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
939 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1176/
Dfsl_pm_device.c891 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
939 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1173/
Dfsl_pm_device.c891 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
939 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()

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