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Searched refs:SYS_PLL1_CTRL (Results 1 – 25 of 45) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_clock.c947 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
951 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
959 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
963 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
971 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
975 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
983 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
987 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
996 reg = ANADIG_PLL->SYS_PLL1_CTRL; in ANATOP_SysPll1WaitStable()
1632 ANADIG_PLL->SYS_PLL1_CTRL = in CLOCK_SetClockSourceControlMode()
[all …]
Dfsl_clock.h1686 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_clock.c947 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
951 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
959 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
963 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
971 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
975 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
983 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
987 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
996 reg = ANADIG_PLL->SYS_PLL1_CTRL; in ANATOP_SysPll1WaitStable()
1632 ANADIG_PLL->SYS_PLL1_CTRL = in CLOCK_SetClockSourceControlMode()
[all …]
Dfsl_clock.h1686 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_clock.c947 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
951 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
959 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
963 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
971 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
975 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
983 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
987 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
996 reg = ANADIG_PLL->SYS_PLL1_CTRL; in ANATOP_SysPll1WaitStable()
1632 ANADIG_PLL->SYS_PLL1_CTRL = in CLOCK_SetClockSourceControlMode()
[all …]
Dfsl_clock.h1686 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_clock.c947 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
951 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
959 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
963 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
971 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
975 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
983 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
987 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
996 reg = ANADIG_PLL->SYS_PLL1_CTRL; in ANATOP_SysPll1WaitStable()
1632 ANADIG_PLL->SYS_PLL1_CTRL = in CLOCK_SetClockSourceControlMode()
[all …]
Dfsl_clock.h1686 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_clock.c1074 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
1078 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
1086 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
1090 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
1098 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
1102 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
1110 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
1114 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
1123 reg = ANADIG_PLL->SYS_PLL1_CTRL; in ANATOP_SysPll1WaitStable()
1194 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK; in CLOCK_GPC_SetSysPll1OutputFreq()
Dfsl_clock.h2243 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_clock.c1074 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
1078 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
1086 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
1090 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
1098 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
1102 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
1110 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
1114 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
1123 reg = ANADIG_PLL->SYS_PLL1_CTRL; in ANATOP_SysPll1WaitStable()
1194 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK; in CLOCK_GPC_SetSysPll1OutputFreq()
Dfsl_clock.h2243 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_clock.c1065 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
1069 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
1077 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
1081 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
1089 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
1093 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
1101 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
1105 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
1114 reg = ANADIG_PLL->SYS_PLL1_CTRL; in ANATOP_SysPll1WaitStable()
1185 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK; in CLOCK_GPC_SetSysPll1OutputFreq()
Dfsl_clock.h2210 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_clock.c1074 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
1078 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
1086 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
1090 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
1098 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
1102 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
1110 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
1114 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
1123 reg = ANADIG_PLL->SYS_PLL1_CTRL; in ANATOP_SysPll1WaitStable()
1194 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK; in CLOCK_GPC_SetSysPll1OutputFreq()
Dfsl_clock.h2243 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_clock.c1074 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
1078 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
1086 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
1090 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
1098 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
1102 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
1110 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
1114 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
1123 reg = ANADIG_PLL->SYS_PLL1_CTRL; in ANATOP_SysPll1WaitStable()
1194 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK; in CLOCK_GPC_SetSysPll1OutputFreq()
Dfsl_clock.h2243 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_clock.c1074 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
1078 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
1086 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
1090 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
1098 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
1102 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
1110 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
1114 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
1123 reg = ANADIG_PLL->SYS_PLL1_CTRL; in ANATOP_SysPll1WaitStable()
1194 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK; in CLOCK_GPC_SetSysPll1OutputFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_clock.c1065 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
1069 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; in ANATOP_SysPll1Gate()
1077 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
1081 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; in ANATOP_SysPll1Div2En()
1089 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
1093 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; in ANATOP_SysPll1Div5En()
1101 ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
1105 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; in ANATOP_SysPll1SwEnClk()
1114 reg = ANADIG_PLL->SYS_PLL1_CTRL; in ANATOP_SysPll1WaitStable()
1185 ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK; in CLOCK_GPC_SetSysPll1OutputFreq()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1175/
Dfsl_pm_device.c883 ANADIG_PLL->SYS_PLL1_CTRL &= ~(ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
931 ANADIG_PLL->SYS_PLL1_CTRL |= (ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1171/
Dfsl_pm_device.c883 ANADIG_PLL->SYS_PLL1_CTRL &= ~(ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
931 ANADIG_PLL->SYS_PLL1_CTRL |= (ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1172/
Dfsl_pm_device.c883 ANADIG_PLL->SYS_PLL1_CTRL &= ~(ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
931 ANADIG_PLL->SYS_PLL1_CTRL |= (ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1176/
Dfsl_pm_device.c883 ANADIG_PLL->SYS_PLL1_CTRL &= ~(ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
931 ANADIG_PLL->SYS_PLL1_CTRL |= (ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1173/
Dfsl_pm_device.c883 ANADIG_PLL->SYS_PLL1_CTRL &= ~(ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
931 ANADIG_PLL->SYS_PLL1_CTRL |= (ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()

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