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Searched refs:SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h25197 #define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK (0x10U) macro
25203 …t32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK)
DMIMXRT685S_cm33.h34810 #define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK (0x10U) macro
34816 …t32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h34810 #define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK (0x10U) macro
34816 …t32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h39534 #define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK (0x10U) macro
39540 …t32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK)
DMIMXRT595S_cm33.h49333 #define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK (0x10U) macro
49339 …t32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h47706 #define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK (0x10U) macro
47712 …t32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h49332 #define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK (0x10U) macro
49338 …t32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK)