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Searched refs:SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h38418 #define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_MASK (0x8000U) macro
38424 …t32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_MASK)
DMIMXRT595S_cm33.h48217 #define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_MASK (0x8000U) macro
48223 …t32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h46590 #define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_MASK (0x8000U) macro
46596 …t32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h48216 #define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_MASK (0x8000U) macro
48222 …t32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_MASK)