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Searched refs:SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h38410 #define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_MASK (0x4000U) macro
38416 …t32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_MASK)
DMIMXRT595S_cm33.h48209 #define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_MASK (0x4000U) macro
48215 …t32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h46582 #define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_MASK (0x4000U) macro
46588 …t32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h48208 #define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_MASK (0x4000U) macro
48214 …t32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_MASK)