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Searched refs:SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h38346 #define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_MASK (0x20U) macro
38352 … << SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_MASK)
DMIMXRT595S_cm33.h48145 #define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_MASK (0x20U) macro
48151 … << SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h46518 #define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_MASK (0x20U) macro
46524 … << SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h48144 #define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_MASK (0x20U) macro
48150 … << SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_MASK)