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Searched refs:SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h37362 #define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_MASK (0x10U) macro
37368 …2_t)(x)) << SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_MASK)
DMIMXRT595S_cm33.h47161 #define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_MASK (0x10U) macro
47167 …2_t)(x)) << SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h45534 #define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_MASK (0x10U) macro
45540 …2_t)(x)) << SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h47160 #define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_MASK (0x10U) macro
47166 …2_t)(x)) << SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_MASK)