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Searched refs:SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h25153 #define SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK (0x80000000U) macro
25159 …(uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK)
DMIMXRT685S_cm33.h34766 #define SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK (0x80000000U) macro
34772 …(uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h34766 #define SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK (0x80000000U) macro
34772 …(uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h39490 #define SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK (0x80000000U) macro
39496 …(uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK)
DMIMXRT595S_cm33.h49289 #define SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK (0x80000000U) macro
49295 …(uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h47662 #define SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK (0x80000000U) macro
47668 …(uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h49288 #define SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK (0x80000000U) macro
49294 …(uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK)