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Searched refs:SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h39410 #define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_MASK (0x20000U) macro
39416 … << SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_MASK)
DMIMXRT595S_cm33.h49209 #define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_MASK (0x20000U) macro
49215 … << SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h47582 #define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_MASK (0x20000U) macro
47588 … << SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h49208 #define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_MASK (0x20000U) macro
49214 … << SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_MASK)