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Searched refs:SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h25017 #define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK (0x1U) macro
25023 …int32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK)
DMIMXRT685S_cm33.h34630 #define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK (0x1U) macro
34636 …int32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h34630 #define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK (0x1U) macro
34636 …int32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h39282 #define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK (0x1U) macro
39288 …int32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK)
DMIMXRT595S_cm33.h49081 #define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK (0x1U) macro
49087 …int32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h47454 #define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK (0x1U) macro
47460 …int32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h49080 #define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK (0x1U) macro
49086 …int32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK)