Searched refs:SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_MASK (Results 1 – 4 of 4) sorted by relevance
39314 #define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_MASK (0x10U) macro39320 … << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_MASK)
49113 #define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_MASK (0x10U) macro49119 … << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_MASK)
47486 #define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_MASK (0x10U) macro47492 … << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_MASK)
49112 #define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_MASK (0x10U) macro49118 … << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_MASK)
