Searched refs:SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_MASK (Results 1 – 4 of 4) sorted by relevance
39298 #define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_MASK (0x4U) macro39304 … << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_MASK)
49097 #define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_MASK (0x4U) macro49103 … << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_MASK)
47470 #define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_MASK (0x4U) macro47476 … << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_MASK)
49096 #define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_MASK (0x4U) macro49102 … << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_MASK)
