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Searched refs:SYSCTL0_FLEXSPI1PADCTL_COMPEN_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h41671 #define SYSCTL0_FLEXSPI1PADCTL_COMPEN_MASK (0x800U) macro
41674 …2_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_COMPEN_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_COMPEN_MASK)
DMIMXRT595S_cm33.h51470 #define SYSCTL0_FLEXSPI1PADCTL_COMPEN_MASK (0x800U) macro
51473 …2_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_COMPEN_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_COMPEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h49843 #define SYSCTL0_FLEXSPI1PADCTL_COMPEN_MASK (0x800U) macro
49846 …2_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_COMPEN_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_COMPEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h51469 #define SYSCTL0_FLEXSPI1PADCTL_COMPEN_MASK (0x800U) macro
51472 …2_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_COMPEN_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_COMPEN_MASK)