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Searched refs:SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (Results 1 – 24 of 24) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/sdif/
Dfsl_sdif.c1671 … SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK); in SDIF_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h14735 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
14739 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h14677 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
14681 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h13885 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
13889 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h14091 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
14095 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h18239 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
18243 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h17006 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
17009 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h18314 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
18318 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h18778 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
18782 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h19160 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
19164 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h18959 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
18963 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h19570 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
19574 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h18778 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
18782 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h17712 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
17715 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54608/
DLPC54608.h18882 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
18886 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h19570 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
19574 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5526/
DLPC5526.h22057 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
22063 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5528/
DLPC5528.h22056 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
22062 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S26/
DLPC55S26.h23713 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
23719 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S28/
DLPC55S28.h23712 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
23718 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S66/
DLPC55S66_cm33_core1.h24333 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
24339 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
DLPC55S66_cm33_core0.h24333 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
24339 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S69/
DLPC55S69_cm33_core1.h24332 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
24338 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
DLPC55S69_cm33_core0.h24332 #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) macro
24338 …(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)