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Searched refs:SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (Results 1 – 23 of 23) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h14729 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
14733 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h14671 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
14675 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h13879 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
13883 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h14085 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
14089 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h18233 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
18237 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h17001 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
17004 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h18308 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
18312 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h18772 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
18776 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h19154 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
19158 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h18953 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
18957 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h19564 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
19568 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h18772 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
18776 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h17707 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
17710 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54608/
DLPC54608.h18876 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
18880 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h19564 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
19568 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5526/
DLPC5526.h22047 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
22055 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5528/
DLPC5528.h22046 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
22054 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S26/
DLPC55S26.h23703 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
23711 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S28/
DLPC55S28.h23702 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
23710 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S66/
DLPC55S66_cm33_core1.h24323 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
24331 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
DLPC55S66_cm33_core0.h24323 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
24331 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S69/
DLPC55S69_cm33_core1.h24322 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
24330 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
DLPC55S69_cm33_core0.h24322 #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) macro
24330 …t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)