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Searched refs:SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h54314 #define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK (0x80U) macro
54320 …(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK)
DMIMXRT735S_cm33_core1.h54374 #define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK (0x80U) macro
54380 …(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK)
DMIMXRT735S_ezhv.h82298 #define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK (0x80U) macro
82304 …(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK)
DMIMXRT735S_cm33_core0.h77398 #define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK (0x80U) macro
77404 …(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h57597 #define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK (0x80U) macro
57603 …(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK)
DMIMXRT758S_hifi1.h57535 #define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK (0x80U) macro
57541 …(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK)
DMIMXRT758S_cm33_core0.h80623 #define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK (0x80U) macro
80629 …(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK)
DMIMXRT758S_ezhv.h85443 #define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK (0x80U) macro
85449 …(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h57535 #define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK (0x80U) macro
57541 …(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK)
DMIMXRT798S_cm33_core1.h57597 #define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK (0x80U) macro
57603 …(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK)
DMIMXRT798S_hifi4.h80536 #define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK (0x80U) macro
80542 …(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK)
DMIMXRT798S_cm33_core0.h80623 #define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK (0x80U) macro
80629 …(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK)
DMIMXRT798S_ezhv.h85467 #define SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK (0x80U) macro
85473 …(((uint32_t)(x)) << SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCON4_VGPU_MEM_CTRL_MEM_STDBY_MASK)