Searched refs:SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK (Results 1 – 13 of 13) sorted by relevance
54350 #define SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK (0x3FFFFFFFU) macro54353 …int32_t)(x)) << SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_SHIFT)) & SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK)
54410 #define SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK (0x3FFFFFFFU) macro54413 …int32_t)(x)) << SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_SHIFT)) & SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK)
82334 #define SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK (0x3FFFFFFFU) macro82337 …int32_t)(x)) << SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_SHIFT)) & SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK)
77434 #define SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK (0x3FFFFFFFU) macro77437 …int32_t)(x)) << SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_SHIFT)) & SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK)
57633 #define SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK (0x3FFFFFFFU) macro57636 …int32_t)(x)) << SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_SHIFT)) & SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK)
57571 #define SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK (0x3FFFFFFFU) macro57574 …int32_t)(x)) << SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_SHIFT)) & SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK)
80659 #define SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK (0x3FFFFFFFU) macro80662 …int32_t)(x)) << SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_SHIFT)) & SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK)
85479 #define SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK (0x3FFFFFFFU) macro85482 …int32_t)(x)) << SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_SHIFT)) & SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK)
80572 #define SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK (0x3FFFFFFFU) macro80575 …int32_t)(x)) << SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_SHIFT)) & SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK)
85503 #define SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK (0x3FFFFFFFU) macro85506 …int32_t)(x)) << SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_SHIFT)) & SYSCON4_EZHV_RSTBASE_EZHV_RSTBASE_MASK)
