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Searched refs:SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h53670 #define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
53676 …(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK)
DMIMXRT735S_cm33_core1.h53730 #define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
53736 …(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK)
DMIMXRT735S_ezhv.h81673 #define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
81679 …(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK)
DMIMXRT735S_cm33_core0.h76754 #define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
76760 …(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h56953 #define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
56959 …(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK)
DMIMXRT758S_hifi1.h56891 #define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
56897 …(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK)
DMIMXRT758S_cm33_core0.h79979 #define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
79985 …(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK)
DMIMXRT758S_ezhv.h84818 #define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
84824 …(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h56891 #define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
56897 …(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK)
DMIMXRT798S_cm33_core1.h56953 #define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
56959 …(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK)
DMIMXRT798S_hifi4.h79892 #define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
79898 …(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK)
DMIMXRT798S_cm33_core0.h79979 #define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
79985 …(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK)
DMIMXRT798S_ezhv.h84842 #define SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) macro
84848 …(((uint32_t)(x)) << SYSCON3_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON3_SWD_ACCESS_CPU_SEC_CODE_MASK)