Searched refs:SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK (Results 1 – 9 of 9) sorted by relevance
52654 #define SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK (0x200U) macro52660 …(((uint32_t)(x)) << SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_SHIFT)) & SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK)
52714 #define SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK (0x200U) macro52720 …(((uint32_t)(x)) << SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_SHIFT)) & SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK)
80695 #define SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK (0x200U) macro80701 …(((uint32_t)(x)) << SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_SHIFT)) & SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK)
55937 #define SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK (0x200U) macro55943 …(((uint32_t)(x)) << SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_SHIFT)) & SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK)
55875 #define SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK (0x200U) macro55881 …(((uint32_t)(x)) << SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_SHIFT)) & SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK)
83840 #define SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK (0x200U) macro83846 …(((uint32_t)(x)) << SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_SHIFT)) & SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK)
83864 #define SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK (0x200U) macro83870 …(((uint32_t)(x)) << SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_SHIFT)) & SYSCON1_EDMA3_EN0_CTIMER5_M1_EN_MASK)
