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Searched refs:SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h52562 #define SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK (0x40000U) macro
52568 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK)
DMIMXRT735S_cm33_core1.h52622 #define SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK (0x40000U) macro
52628 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK)
DMIMXRT735S_ezhv.h80603 #define SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK (0x40000U) macro
80609 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h55845 #define SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK (0x40000U) macro
55851 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK)
DMIMXRT758S_hifi1.h55783 #define SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK (0x40000U) macro
55789 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK)
DMIMXRT758S_ezhv.h83748 #define SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK (0x40000U) macro
83754 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h55783 #define SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK (0x40000U) macro
55789 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK)
DMIMXRT798S_cm33_core1.h55845 #define SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK (0x40000U) macro
55851 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK)
DMIMXRT798S_ezhv.h83772 #define SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK (0x40000U) macro
83778 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA1_EN_MASK)