Home
last modified time | relevance | path

Searched refs:SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h52554 #define SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK (0x20000U) macro
52560 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK)
DMIMXRT735S_cm33_core1.h52614 #define SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK (0x20000U) macro
52620 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK)
DMIMXRT735S_ezhv.h80595 #define SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK (0x20000U) macro
80601 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h55837 #define SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK (0x20000U) macro
55843 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK)
DMIMXRT758S_hifi1.h55775 #define SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK (0x20000U) macro
55781 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK)
DMIMXRT758S_ezhv.h83740 #define SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK (0x20000U) macro
83746 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h55775 #define SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK (0x20000U) macro
55781 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK)
DMIMXRT798S_cm33_core1.h55837 #define SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK (0x20000U) macro
55843 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK)
DMIMXRT798S_ezhv.h83764 #define SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK (0x20000U) macro
83770 …(uint32_t)(x)) << SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_SHIFT)) & SYSCON1_EDMA2_EN1_GPIO10_DMA0_EN_MASK)