Home
last modified time | relevance | path

Searched refs:SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h52214 #define SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK (0x20U) macro
52220 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK)
DMIMXRT735S_cm33_core1.h52274 #define SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK (0x20U) macro
52280 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK)
DMIMXRT735S_ezhv.h80255 #define SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK (0x20U) macro
80261 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h55497 #define SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK (0x20U) macro
55503 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK)
DMIMXRT758S_hifi1.h55435 #define SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK (0x20U) macro
55441 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK)
DMIMXRT758S_ezhv.h83400 #define SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK (0x20U) macro
83406 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h55435 #define SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK (0x20U) macro
55441 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK)
DMIMXRT798S_cm33_core1.h55497 #define SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK (0x20U) macro
55503 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK)
DMIMXRT798S_ezhv.h83424 #define SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK (0x20U) macro
83430 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_PINT1_IRQ1_EN_MASK)