Searched refs:SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK (Results 1 – 9 of 9) sorted by relevance
52246 #define SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK (0x200U) macro52252 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK)
52306 #define SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK (0x200U) macro52312 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK)
80287 #define SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK (0x200U) macro80293 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK)
55529 #define SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK (0x200U) macro55535 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK)
55467 #define SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK (0x200U) macro55473 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK)
83432 #define SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK (0x200U) macro83438 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK)
83456 #define SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK (0x200U) macro83462 …(((uint32_t)(x)) << SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_SHIFT)) & SYSCON1_EDMA2_EN0_CTIMER5_M1_EN_MASK)
