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Searched refs:SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h78099 #define SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK (0x40000000U) macro
78105 …(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK)
DMIMXRT798S_cm33_core0.h78186 #define SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK (0x40000000U) macro
78192 …(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK)
DMIMXRT798S_ezhv.h81828 #define SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK (0x40000000U) macro
81834 …(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h78659 #define SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK (0x40000000U) macro
78665 …(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK)
DMIMXRT735S_cm33_core0.h74961 #define SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK (0x40000000U) macro
74967 …(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h78186 #define SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK (0x40000000U) macro
78192 …(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK)
DMIMXRT758S_ezhv.h81804 #define SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK (0x40000000U) macro
81810 …(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO3_DMA1_EN_MASK)