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Searched refs:SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h78083 #define SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK (0x10000000U) macro
78089 …(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK)
DMIMXRT798S_cm33_core0.h78170 #define SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK (0x10000000U) macro
78176 …(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK)
DMIMXRT798S_ezhv.h81812 #define SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK (0x10000000U) macro
81818 …(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h78643 #define SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK (0x10000000U) macro
78649 …(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK)
DMIMXRT735S_cm33_core0.h74945 #define SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK (0x10000000U) macro
74951 …(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h78170 #define SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK (0x10000000U) macro
78176 …(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK)
DMIMXRT758S_ezhv.h81788 #define SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK (0x10000000U) macro
81794 …(((uint32_t)(x)) << SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_SHIFT)) & SYSCON0_EDMA1_EN2_GPIO2_DMA1_EN_MASK)