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Searched refs:SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h77395 #define SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK (0x80U) macro
77401 …2_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_XSPI2_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK)
DMIMXRT798S_cm33_core0.h77482 #define SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK (0x80U) macro
77488 …2_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_XSPI2_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK)
DMIMXRT798S_ezhv.h81124 #define SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK (0x80U) macro
81130 …2_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_XSPI2_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h77955 #define SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK (0x80U) macro
77961 …2_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_XSPI2_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK)
DMIMXRT735S_cm33_core0.h74257 #define SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK (0x80U) macro
74263 …2_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_XSPI2_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h77482 #define SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK (0x80U) macro
77488 …2_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_XSPI2_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK)
DMIMXRT758S_ezhv.h81100 #define SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK (0x80U) macro
81106 …2_t)(((uint32_t)(x)) << SYSCON0_EDMA1_EN0_XSPI2_TX_EN_SHIFT)) & SYSCON0_EDMA1_EN0_XSPI2_TX_EN_MASK)