Searched refs:SW_PAD_CTL_PAD_SD3_DATA5 (Results 1 – 2 of 2) sorted by relevance
15994 __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA5; /**< Pad Control Register, offset: 0x5B4 */ member16543 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA5)
21920 …__IO uint32_t SW_PAD_CTL_PAD_SD3_DATA5; /**< SW_PAD_CTL_PAD_SD3_DATA5 SW PAD Contro… member22391 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA5)
