Searched refs:SW_PAD_CTL_PAD_SD3_DATA1 (Results 1 – 2 of 2) sorted by relevance
15990 __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA1; /**< Pad Control Register, offset: 0x5A4 */ member16539 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA1)
21916 …__IO uint32_t SW_PAD_CTL_PAD_SD3_DATA1; /**< SW_PAD_CTL_PAD_SD3_DATA1 SW PAD Contro… member22387 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA1)
