Searched refs:SW_PAD_CTL_PAD_SD3_DATA0 (Results 1 – 2 of 2) sorted by relevance
15989 __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA0; /**< Pad Control Register, offset: 0x5A0 */ member16538 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA0)
21915 …__IO uint32_t SW_PAD_CTL_PAD_SD3_DATA0; /**< SW_PAD_CTL_PAD_SD3_DATA0 SW PAD Contro… member22386 #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA0)
