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Searched refs:SW_PAD_CTL_PAD_GPIO1_IO12 (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h15856 __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO12; /**< Pad Control Register, offset: 0x38C */ member
16405 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO12)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h21800 …__IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO12; /**< SW_PAD_CTL_PAD_GPIO1_IO12 SW PAD Contr… member
22271 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO12)