Searched refs:SW_PAD_CTL_PAD_GPIO1_IO07 (Results 1 – 2 of 2) sorted by relevance
15851 __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO07; /**< Pad Control Register, offset: 0x378 */ member16400 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO07)
27251 …__IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO07; /**< SW_PAD_CTL_PAD_GPIO1_IO07 SW PAD Contr… member27283 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO07)
