Searched refs:SW_PAD_CTL_PAD_GPIO1_IO05 (Results 1 – 2 of 2) sorted by relevance
15849 __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO05; /**< Pad Control Register, offset: 0x370 */ member16398 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO05)
27249 …__IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO05; /**< SW_PAD_CTL_PAD_GPIO1_IO05 SW PAD Contr… member27281 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO05)
