Searched refs:SW_PAD_CTL_PAD_GPIO1_IO04 (Results 1 – 2 of 2) sorted by relevance
15848 __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO04; /**< Pad Control Register, offset: 0x36C */ member16397 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO04)
27248 …__IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO04; /**< SW_PAD_CTL_PAD_GPIO1_IO04 SW PAD Contr… member27280 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO04)
