Searched refs:SW_PAD_CTL_PAD_GPIO1_IO03 (Results 1 – 2 of 2) sorted by relevance
15847 __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO03; /**< Pad Control Register, offset: 0x368 */ member16396 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO03)
27247 …__IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO03; /**< SW_PAD_CTL_PAD_GPIO1_IO03 SW PAD Contr… member27279 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO03)
